Analysis and visualization of application concurrency and processor resource utilization

• US 9,594,656 B2
• Filed: 10/26/2009
• Issued: 03/14/2017
• Est. Priority Date: 10/26/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Shafi, Hazim
• Primary Examiner(s): Lee, Tammy
• Application Number:
  US12/605,932
• Publication Number:
  US 20110099554A1
• Time in Patent Office: 2,696 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3017 where the computing system is implementing multitasking multiprogramming arrangements G06F9/46; allocation of resources G06F9/50
• CPC Class Codes: G06F 11/302 where the computing system component is a software system
• CPC Class Codes: G06F 11/3072 where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting
• CPC Class Codes: G06F 11/32 with visual or acoustical indication of the functioning of the machine
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software

Abstract

An analysis and visualization depicts how an application is leveraging computer processor cores in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime. Information regarding processes or threads running on the processor cores over time is received, analyzed, and presented to indicate portions of processor cores that are used by the application, idle, or used by other processes in the system. The analysis and visualization can help a developer understand contention for processor resources, confirm the degree of concurrency, or identify serial regions of execution that might provide opportunities for exploiting parallelism.

Claims

1. A computing device implemented method, comprising:

receiving a plurality of context switch records and a total number of logical cores in a processing system, the context switch records are generated by recording context switches developed from executing a plurality of threads of at least one selected process in a concurrent application;

extracting from the context switch records a number of the logical cores used to perform the at least one selected process over a course of time;

separating the course of time into periodic intervals;

determining a representative number of logical cores executing the selected process for each of the periodic intervals;

presenting the representative number of logical cores executing the selected process for each of the periodic intervals against the total number of logical cores over the course of time to display contention for processor resources and how the contention for processor resources varies with time identifying varying degrees of parallelism in the at least one selected process; and

identifying corresponding sections of code executing the selected process for modification.

2. The method of claim 1 wherein the plurality of context switch records are determined with an enabled trace conducted over a duration of the trace.

3. The method of claim 1 wherein the context switch records include information regarding concurrently executing processes and information associating threads to the concurrently executing processes.

4. The method of claim 1 wherein the context switch records include context switch events.

5. The method of claim 4 wherein the context switch records are representative of threads executing in the selected process.

6. The method of claim 5 wherein the representative number includes the average number of concurrently executing threads in the selected process over the course of the periodic interval.

7. The method of claim 1 wherein the selected process includes at least two separate selected processes.

8. The method of claim 7 where in the at least two separate selected processes includes a process of interest, an idle process, and a system process.

9. The method of claim 1 wherein a number of a logical cores used to perform other processes are determined from subtracting the number of the logical cores used to perform the selected process from the total number of logical cores at a given time.

10. The method of claim 1 wherein the representative number of logical cores for each of the periodic intervals against the total number of logical cores over the course of time is presented in an area graph.

11. A computer readable storage medium, which does not includes a transitory propagating signal, storing computer executable instructions for controlling a computing device to perform a method comprising:

receiving a plurality of context switch records and a total number of logical cores in a processing system, the context switch records are generated by recording context switches developed from executing a plurality of threads in at least one selected process of a concurrent application;

extracting from the context switch records a number of the logical cores used to perform the selected process over a course of time;

extracting from the context switch records a number of the logical cores used to perform an idle process over a course of time;

separating the course of time into periodic intervals;

determining a representative number of logical cores executing each of the selected and idle processes for each of the periodic intervals;

determining a representative number of logical cores executing other processes for each of the periodic intervals;

presenting the representative number of logical cores executing the selected process, the idle process, and the other processes for each of the periodic intervals against the total number of logical cores over the course of time to display contention for processor resources and how the contention for processor resources varies with time identifying regions of contention in the at least one selected process in a visualization; and

linking corresponding sections of code of the selected process for modification to the visualization.

12. The computer readable storage medium of claim 11 wherein the total number of logical cores in the processing system are received by causing an operating system to interrogate the processing system.

13. The computer readable storage medium of claim 11 wherein a trace is enabled over a duration of time in the operating system to receive the plurality of context switch records.

14. The computer readable medium of claim 13 wherein the separating the course of time into periodic intervals includes separating the duration of time into equal intervals of time.

15. The computer readable storage medium of claim 11 further including an integrated development environment.

16. The computer readable storage medium of claim 15 wherein integrated development environment includes a code editor, a compiler, build tools, and a debugger.

17. The computer readable storage medium of claim 15 wherein the presenting includes providing a link to additional information in regarding the concurrent processes in the integrated developer environment.

18. The computer readable storage medium of claim 11 wherein determining the representative number of logical cores executing other processes for each of the periodic intervals includes subtracting the sum of the representative numbers of the logical cores used to perform the selected process and the idle process from the total number of logical cores for a given periodic interval.

19. A system, comprising:

a processor;

a memory storing instructions executable by the processor to;

receive a plurality of context switch records, the context switch records are generated with a trace recording context switches and developed from executing a plurality of threads in at least one selected process of a concurrent application over a duration of time;

separate the duration of time into equal periodic intervals of time;

extract from the context switch records a number of the plurality of logical cores used to perform the selected process over the duration of time;

extract from the context switch records a number of the logical cores used to perform an idle process over the duration of time;

extract from the context switch records a number of the logical cores used to perform a system process over the duration of time;

determine a representative number of logical cores executing each of the selected process, idle process, and system process for each of the periodic intervals of time;

determine a representative number of logical cores executing other processes for each of the periodic intervals of time including subtracting the sum of the representative numbers of the logical cores used to perform the selected process, the idle process, and the system process from the total number of logical cores for a given periodic interval of time;

present the representative number of logical cores executing the selected process, the idle process, the system process, and the other processes for each of the periodic intervals in an area graph to display contention for processor resources and how the contention for processor resources varies with time and identify degrees of parallelism in the area graph; and

link corresponding sections of code available for modification to user-selected portions of the area graph.

20. The system of claim 19 and further comprising linking additional details to user-selected portions of the area graph.