Data processing in a multiple processor system to maintain multiple processor cache memory access coherency

• US 9,594,683 B2
• Filed: 11/17/2014
• Issued: 03/14/2017
• Est. Priority Date: 12/03/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schuh, Stefan, Dittrich, Jens, Jacobi, Christian, Pflanz, Matthias, Weber, Kai
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US14/543,319
• Publication Number:
  US 20150154116A1
• Time in Patent Office: 848 Days
• Field of Search: 711/122
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache

Abstract

A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover is positioned closer to the main memory and is connected to the cache memories of the at least one shared cache level (L2, L3, L4), the main memory and to the multiple processors to move data between the cache memories of the at least one shared cache level, the main memory and the processors. In response to a request from one of the processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories and the main memory maintaining multiple processor cache memory access coherency.

Claims

1. A data processing system comprising:

at least one page mover positioned closer to a main memory of multiple processors and is connected to cache memories of at least one cache level shared between the multiple processors, the main memory and to multiple processors to move data between the cache memories of the at least one cache level, the main memory and the multiple processors, wherein in response to a request from one requesting processor of the multiple processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories;

the cache memories of the at least one cache level or the main memory maintaining multiple processor cache memory access coherency;

wherein the at least one page mover comprises a data processing engine which performs filtering of the fetched data, wherein the data processing engine comprises at least one filter engine to filter data of a storage area line-wise by comparing elements of a fetched line from a source address of one or more of the at least one cache level or the main memory with filter arguments to create a bitmask, and to write comparison results as bitmask data in a bitmask buffer of a target storage area located at a target address of one or more of the at least one cache level or the main memory based on a corresponding request from one processor of the multiple processors containing a filter command with the filter arguments and source and target information; and

wherein the page mover moves processed data to at least one of the following components;

cache memories of the at least one cache level, the main memory or the requesting processor maintaining multiple processor cache memory access coherency.

2. The data processing system according to claim 1, wherein said data processing engine comprises at least one filter engine to move data of a storage area corresponding with bitmask data of said bitmask buffer line-wise from a source address to a target address to create a bitmask data set based on a corresponding request from one processor of said multiple processors containing a move command and bitmask and source and target information.

3. The data processing system according to claim 2, wherein the at least one page mover comprises a data processing engine which performs aggregation of the fetched data, and wherein the data processing engine comprises at least one aggregation engine to perform arithmetic or boolean operations with data of at least one storage area fetched from a corresponding source address having a corresponding bitmask data set and to send a data processing result to a storage area at a target address of the one or more of the at least one cache level or the main memory or to a requesting processor based on a corresponding request from one processor of the multiple processors containing an aggregation command and bitmask and source and target information.

4. The data processing system according to claim 2, wherein the at least one page mover comprises a data processing engine which performs aggregation of the fetched data, and wherein the data processing engine comprises at least one aggregation engine to perform arithmetic or boolean operations with data of a first storage area fetched from corresponding source addresses having a corresponding first bitmask data set, and data of a second storage area fetched from corresponding source addresses having said corresponding bitmask set, and to send a data processing result to a storage area at target addresses of one or more of said at least one cache level or said main memory or to a requesting processor based on a corresponding request from one processor of said multiple processors containing an aggregation command and bitmask and source and target information.

5. A method of data processing in a multiple processor system with a hierarchical cache structure comprising multiple levels of cache between multiple processors and a main memory of the multiple processors, wherein at least cache memories of one cache level are shared between said multiple processors, said method comprising:

based on a request from one processor of said multiple processors, fetching data of a storage area line-wise from at least one of the following memories;

said cache memories of said at least one cache level or said main memory to at least one page mover maintaining multiple processor cache memory access coherency;

performing data processing operations comprising filtering of said fetched data in the at least one page mover, said at least one page mover positioned closer to said main memory and connected to said cache memories of said at least one cache level, said main memory and to said multiple processors to move data between said cache memories of said at least one cache level, said main memory or said multiple processors, the filtering comprising, based on a request from one processor of said multiple processors containing a filter command with filter arguments and source and target information data of a storage area, filtering line-wise by comparing elements of a fetched line from a source address of said at least one cache level or said main memory with filter arguments, wherein comparison results are written in a bitmask buffer located at a target address of said at least one cache level or said main memory; and

moving processed data from said at least one page mover to at least one of the following components;

cache memories of said at least one cache level, said main memory or the requesting processor maintaining multiple processor cache memory access coherency.

6. The method according to claim 5, further comprising moving data of a storage area line-wise from a source address of said at least one cache level or said main memory to a target address of said at least one cache level or said main memory based on a corresponding request from one processor of said multiple processors containing a move command and source and target information.

7. The method according to claim 5, the performing data processing operations further comprising aggregating, the aggregating comprising:

based on a request from one processor of said multiple processors containing an aggregation command and source and target information, performing arithmetic or boolean operations with data of at least one storage area fetched from a corresponding source address of said at least one cache level or said main memory, wherein a data processing result is sent to a storage area at a target address of said at least one cache level or said main memory or to a requesting processor.

8. The method according to claim 7, wherein at least one aggregation engine performs arithmetic or boolean operations with data of a first storage area and a masked or unmasked second storage area fetched from corresponding source addresses of said at least one cache level or said main memory.

9. A computer program product for data processing in a multiple processor system with a hierarchical cache structure comprising multiple levels of cache between multiple processors and a main memory of the multiple processors, wherein at least cache memories of one cache level are shared between said multiple processors, said computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

based on a request from one processor of said multiple processors, fetching data of a storage area line-wise from at least one of the following memories;

said cache memories of said at least one cache level or said main memory to at least one page mover maintaining multiple processor cache memory access coherency;

performing data processing comprising filtering of said fetched data in the at least one page mover, said at least one page mover positioned closer to said main memory and connected to said cache memories of said at least one cache level, said main memory and to said multiple processors to move data between said cache memories of said at least one cache level, said main memory or said multiple processors, the filtering comprising, based on a request from one processor of said multiple processors containing a filter command with filter arguments and source and target information data of a storage area, filtering line-wise by comparing elements of a fetched line from a source address of said at least one cache level or said main memory with filter arguments, wherein comparison results are written in a bitmask buffer located at a target address of said at least one cache level or said main memory; and

moving processed data from said at least one page mover to at least one of the following components;

cache memories of said at least one cache level, said main memory or the requesting processor maintaining multiple processor cache memory access coherency.

10. The computer program product according to claim 9, wherein said method further comprises moving data of a storage area line-wise from a source address of said at least one cache level or said main memory to a target address of said at least one cache level or said main memory based on a corresponding request from one processor of said multiple processors containing a move command and source and target information.

11. The computer program product according to claim 9, the performing data processing operations further comprising aggregating, the aggregating comprising:

based on a request from one processor of said multiple processors containing an aggregation command and source and target information, performing arithmetic or boolean operations with data of at least one storage area fetched from a corresponding source address of said at least one cache level or said main memory, wherein a data processing result is sent to a storage area at a target address of said at least one cache level or said main memory or to a requesting processor.

12. The computer program product according to claim 11, wherein at least one aggregation engine performs arithmetic or boolean operations with data of a first storage area and a masked or unmasked second storage area fetched from corresponding source addresses of said at least one cache level or said main memory.