Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements

• US 9,594,723 B2
• Filed: 03/13/2013
• Issued: 03/14/2017
• Est. Priority Date: 11/30/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Master, Paul L., Smith, Stephen J., Watson, John
• Primary Examiner(s): Vicary, Keith
• Application Number:
  US13/799,393
• Publication Number:
  US 20130304960A1
• Time in Patent Office: 1,462 Days
• Field of Search: 326 37- 41
• US Class Current: 1/1
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.

Claims

1. A system for adaptive configuration, the system comprising:

a memory storing configuration information, the configuration information including a first configuration information for performing a first function and a second configuration information for performing a second function;

a first computational unit including a first plurality of heterogeneous computational elements and a first interconnection network coupling the first plurality of heterogeneous computational elements together, the first interconnection network changing interconnections between the first plurality of heterogeneous computational elements in response to the first configuration information to perform the first function, wherein each heterogeneous computational element of the first plurality of heterogeneous computational elements is a fixed application specific circuit having a corresponding logic gate layout to perform a specific function;

a second computational unit including a second plurality of heterogeneous computational elements and a second interconnection network coupling the second plurality of heterogeneous computational elements together, the second interconnection network changing interconnections between the second plurality of heterogeneous computational elements in response to the second configuration information to perform the second function, wherein each heterogeneous computational element of the second plurality of heterogeneous computational elements is a fixed application specific circuit having a corresponding logic gate layout to perform a specific function; and

wherein in response to receiving the second configuration information, the first interconnection network changes interconnections between at least some of the first plurality of heterogeneous computational elements to perform the second function and the second interconnection network changes interconnections between at least some of the second plurality of heterogeneous computational elements to perform the second function.

2. The system of claim 1, wherein the memory comprises a third plurality of heterogeneous computational elements configured to perform a memory function.

3. The system of claim 1, wherein the system is embodied within an integrated circuit, and wherein the integrated circuit does not comprise an array of identical logical units.

4. The system of claim 1, wherein the first plurality of heterogeneous computational elements includes at least one of a function generator, an adder and a register, the function generator having data inputs and a control input to select a specific function.

5. The system of claim 1, wherein the second plurality of heterogeneous computational elements includes a multiplier, an adder, and a register.

6. The system of claim 1, wherein one of the first plurality of heterogeneous computational elements in one location is configured while the second function is performed.

7. The system of claim 1, wherein the first plurality of heterogeneous computational elements comprises an adder, and wherein the second plurality of heterogeneous computational elements comprises a multiplier.

8. The system of claim 1, wherein the first function is memory management, and the second function is multiplication.

9. The system of claim 1, wherein the first plurality of heterogeneous computational elements have fixed and differing architectures, and wherein the second plurality of heterogeneous computational elements have fixed and differing architectures.

10. The system of claim 1, wherein one of the first plurality of heterogeneous computational elements has a first fixed architecture, and wherein one of the second plurality of heterogeneous computational elements has a second fixed architecture, the first fixed architecture being different than the second fixed architecture.

11. A method for adaptive configuration of a system, the system including a first computational unit including a first plurality of heterogeneous computational elements and a first interconnection network coupling the first plurality of heterogeneous computational elements together and a second computational unit including a second plurality of heterogeneous computational elements and a second interconnection network coupling the second plurality of heterogeneous computational elements together, the method comprising:

storing configuration information in a memory, the configuration information including a first configuration information for performing a first function and a second configuration information for performing a second function;

changing interconnections of the first interconnection network between the first plurality of heterogeneous computational elements in response to the first configuration information to perform the first function, wherein the first plurality of heterogeneous computational elements have fixed and differing architectures;

changing interconnections of the second interconnection network between the second plurality of heterogeneous computational elements in response to the second configuration information to perform the second function, wherein the second plurality of heterogeneous computational elements have fixed and differing architectures; and

in response to receiving the second configuration information, changing interconnections of the first interconnection network between at least some of the first plurality of heterogeneous computational elements to perform the second function and changing interconnections of the second interconnection network between at least some of the second plurality of heterogeneous computational elements to perform the second function.

12. The method of claim 11, wherein the memory comprises a third plurality of heterogeneous computational elements configured to perform a memory function.

13. The method of claim 11, wherein the memory and the first and the second computational units are embodied within an integrated circuit.

14. The method of claim 11, wherein the first plurality of heterogeneous computational elements includes at least one of a function generator, an adder and a register, the function generator having data inputs and a control input to select a specific function.

15. The method of claim 11, wherein the second plurality of heterogeneous computational elements includes a multiplier, an adder, and a register.

16. A configurable integrated circuit comprising:

a memory storing configuration information, the configuration information including a first configuration information for performing a first function and a second configuration information for performing a second function;

a computational unit including a plurality of heterogeneous computational elements and an interconnection network coupling the plurality of heterogeneous computational elements together, the interconnection network changing interconnections between the plurality of heterogeneous computational elements in response to the first configuration information to perform the first function, wherein each heterogeneous computational element of the plurality of heterogeneous computational elements is a fixed application specific circuit having a corresponding logic gate layout to perform a specific function; and

wherein in response to receiving the second configuration information, the interconnection network changes interconnections between at least some of the plurality of heterogeneous computational elements to perform the second function.

17. The configurable integrated circuit of claim 16, wherein one of the plurality of heterogeneous computational elements in one location is configured while the second function is performed.

18. The configurable integrated circuit of claim 16, wherein the second configuration information is received after completion of the first function and wherein the at least some of the plurality of heterogeneous computational elements to perform the second function perform the first function.

19. The configurable integrated circuit of claim 16, wherein the plurality of heterogeneous computational elements includes at least one of a function generator, an adder and a register, the function generator having data inputs and a control input to select a specific function.

20. The configurable integrated circuit of claim 16, wherein the plurality of heterogeneous computational elements includes a multiplier, an adder, and a register.