Providing a trusted execution environment using a processor

• US 9,594,927 B2
• Filed: 09/10/2014
• Issued: 03/14/2017
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Barry, Peter J., Poornachandran, Rajesh, Van De Ven, Arjan, Dice, Peter A., Selvaraje, Gopinatth, Carreno, Julien, Rosenbaum, Lee G.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ERDMAN, CHAD G
• Application Number:
  US14/482,136
• Publication Number:
  US 20160070932A1
• Time in Patent Office: 916 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/53 by executing in a restricted environment, e.g. sandbox or secure virtual machine
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/033 Test or assess software
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 2221/2111 Location-sensitive, e.g. geographical location, GPS
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: H04L 2209/60 Digital content management, e.g. content distribution
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms
• CPC Class Codes: H04L 9/302 involving the integer factorization problem, e.g. RSA or quadratic sieve [QS] schemes

Abstract

In an embodiment, a system on a chip includes: a single core to execute a legacy instruction set, the single core configured to enter a system management mode (SMM) to provide a trusted execution environment to perform at least one secure operation; and a memory controller coupled to the single core, the memory controller to interface with a system memory, where a portion of the system memory comprises a secure memory for the SMM, and the single core is to authenticate and execute a boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory. Other embodiments are described and claimed.

Claims

1. A system on a chip (SoC) comprising:

a single core to execute a legacy instruction set, wherein the single core comprises the only core of the SoC, and wherein the single core is configured to enter a system management mode (SMM) to provide a trusted execution environment (TEE) to perform at least one secure operation, wherein in the TEE, the single core is to emulate at least one security instruction of an instruction set unsupported by the single core; and

a memory controller coupled to the single core, the memory controller to interface with a system memory, wherein a portion of the system memory comprises a secure memory for the SMM, and wherein the single core is to authenticate a boot firmware, execute the boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory.

2. The SoC of claim 1, wherein the single core is to operate in the SMM to obtain the key pair from the protected storage comprising a non-volatile storage including an isolated key store to store the key pair, wherein the key pair is to be generated and stored in the non-volatile storage during manufacture of a system including the SoC.

3. The SoC of claim 2, wherein the secure memory is to be reset on reset of the SoC such that the key pair is deleted, the secure memory to be isolated from access outside of the SMM.

4. The SoC of claim 1, wherein in the TEE, the single core is to receive encrypted content, decrypt the encrypted content using one or more derived keys stored in an unprotected storage coupled to the SoC, and output the decrypted content to an output device via a trusted channel.

5. The SoC of claim 1, wherein in the TEE, the single core is to encrypt a page of information stored in the secure memory and store the encrypted page in an unprotected portion of the system memory.

6. The SoC of claim 1, wherein the SoC further comprises a boot read only memory (ROM) to store the key pair in a protected portion of the boot ROM.

7. The SoC of claim 1, wherein the single core is to pass execution from the SMM to an operating system to be booted after the key pair is stored in the secure memory.

8. At least one computer non-transitory readable medium including instructions that when executed cause a system to:

execute at least a portion of a firmware of a pre-boot environment in a single core of a processor to create a trusted portion of a system memory, wherein the single core comprises the only core of a system on a chip (SOC);

transfer execution to a trusted agent associated with the trusted portion;

enter a trusted execution environment via the trusted agent;

emulate at least one security instruction of an instruction set unsupported by the single core while in the trusted execution environment;

request a key pair from a protected portion of a non-volatile storage, store the key pair in the trusted portion of the system memory, and thereafter transfer execution from the trusted agent to an operating system.

9. The at least one computer readable medium of claim 8, further comprising instructions that when executed enable the system to receive a trusted action request from a non-trusted agent, and if the trusted action request is supported by the trusted agent, execute a secure operation corresponding to the trusted action request in the trusted execution environment.

10. The at least one computer readable medium of claim 8, further comprising instructions that when executed enable the system to request the key pair from the protected portion of the non-volatile memory responsive to an IN₁₃ SMM instruction executed by the single core, while in a trusted execution environment.

11. The at least one computer readable medium of claim 8, further comprising instructions that when executed enable the system to receive encrypted content, decrypt the encrypted content using one or more derived keys stored in the system memory, and output the decrypted content to an output device via a trusted channel.

12. The at least one computer readable medium of claim 8, further comprising instructions that when executed enable the system to encrypt a page of information stored in the trusted portion of the system memory and store the encrypted page in an unprotected portion of the system memory.

13. A system comprising:

a processor having a single core to execute a legacy instruction set, wherein the single core comprises the only core of the processor, and wherein the single core is configured to enter a system management mode (SMM) to instantiate a trusted execution environment (TEE), the single core further having a secure storage and a memory controller to interface with a memory, wherein the memory comprises a secure portion for the SMM, and wherein the single core is to authenticate a boot firmware, execute the boot firmware, and pass control to the SMM to obtain an endorsement key from the secure storage and store the endorsement key in the secure portion of the memory, and wherein in the TEE, the single core is to emulate at least one security instruction of an instruction set unsupported by the single core;

a display device coupled to the processor, the display device including a frame buffer to store processed data to be displayed on the display device; and

the memory coupled to the processor, the memory including the secure portion to store the endorsement key and an unprotected portion to store one or more decryption keys, wherein in the TEE the processor is to receive encrypted content, decrypt the encrypted content using the one or more decryption keys, and output the decrypted content to the display device.

14. The system of claim 13, wherein the display device is coupled to the processor via a trusted channel, wherein the processor is to execute a display driver in the TEE to pass the processed data to the display device for storage in the frame buffer.

15. The system of claim 13, wherein the endorsement key comprises a storage root key, the processor to use the storage root key to encrypt the one or more decryption keys prior to storage in the unprotected portion of the memory.

16. The system of claim 14, wherein the secure storage comprises an on-chip read only memory (ROM), the on-chip ROM further to store at least a portion of the boot firmware.

17. The system of claim 14, wherein the secure storage comprises a set of programmable fuses of the processor.

18. The system of claim 14, wherein in the TEE, the processor is to encrypt a page of information stored in the secure portion of the memory and store the encrypted page in the unprotected portion of the memory.