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Nonvolatile semiconductor memory device

  • US 9,595,337 B2
  • Filed: 09/26/2016
  • Issued: 03/14/2017
  • Est. Priority Date: 11/29/2010
  • Status: Active Grant
First Claim
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1. A memory device, comprisinga memory cell array including a first block, the first block including a first group and a second group, the first group including a first unit and a second unit, the second group including a third unit and a fourth unit, a gate of a drain side selection transistor in the first unit being coupled to a gate of a drain side selection transistor in the second unit, a gate of a drain side selection transistor in the third unit being coupled to a gate of a drain side selection transistor in the fourth unit, gates of memory cells in the first to third unit being coupled to a gate of a memory cell in the fourth unit,wherein the memory device is capable of selectively erasing data stored in either the first group or the second group.

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