Early prediction of failure in programming a nonvolatile memory

• US 9,595,343 B1
• Filed: 06/05/2016
• Issued: 03/14/2017
• Est. Priority Date: 06/05/2016
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Gurgi, Eyal, Srinivasan, Charan
• Primary Examiner(s): Le, Vu
• Application Number:
  US15/173,655
• Time in Patent Office: 282 Days
• Field of Search: 365/185.18, 365/185.28, 365/185.22
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A storage device includes multiple memory cells and storage circuitry. The storage circuitry is configured to write data to a group of the memory cells by applying to the group of the memory cells up to a maximal number of programming pulses. The storage circuitry is further configured to evaluate, after applying less than the maximal number of programming pulses, a criterion that predicts whether or not the data will be written successfully within the maximal number of programming pulses, and when the criterion predicts that writing the data will fail, to perform a corrective operation.

Claims

1. A storage device, comprising:

multiple memory cells; and

storage circuitry, which is configured to;

write data to a group of the memory cells by applying to the group of the memory cells up to a maximal number of programming pulses;

after applying less than the maximal number of programming pulses, evaluating a criterion that predicts whether or not the data will be written successfully within the maximal number of programming pulses; and

when the criterion predicts that writing the data will fail, perform a corrective operation.

2. The storage device according to claim 1, wherein the storage circuitry is configured to:

evaluate the criterion by estimating a trend of a parameter measured over multiple programming pulses, wherein the parameter is indicative of a number of the memory cells in the group that have not yet reached their target levels.

3. The storage device according to claim 2, wherein the parameter comprises measurements of an electrical current consumed during respective programming pulses.

4. The storage device according to claim 2, wherein the parameter comprises numbers of memory cells that are inhibited from further programming after applying respective programming pulses.

5. The storage device according to claim 2, wherein the storage circuitry is configured to:

estimate the trend by calculating differences between values of the parameter corresponding to different respective programming pulses; and

predict that writing the data will fail based on the differences.

6. The storage device according to claim 2, wherein the storage circuitry is configured to:

hold a reference parameter;

calculate a distance metric between the parameter and the reference parameter; and

predict that writing the data will fail when the distance metric exceeds a given distance threshold.

7. The storage device according to claim 1, wherein the storage circuitry is configured to:

evaluate the criterion by measuring an elapsed programming time since a starting time of writing the data; and

predict that writing the data will fail when the elapsed programming time exceeds a given timeout limit.

8. The storage according to claim 7, wherein the storage circuitry is configured to determine the given timeout limit based on statistical properties of programming execution times.

9. The storage device according to claim 1, wherein the group of the memory cells comprises multiple subgroups that belong to different respective planes of the storage device, and wherein the storage circuitry is configured to:

write the data using a multi-plane programming operation that applies the programming pulses to the memory cells in the multiple subgroups in parallel; and

perform the corrective operation by applying a single-plane programming to at least one of the planes.

10. The storage device according to claim 9, wherein the storage circuitry is configured to:

measure first and second parameters for respective first and second planes; and

predict that writing the data will fail in at least one of the first and second planes by evaluating the criterion based on both the first and second parameters.

11. A method for data storage, comprising:

in a storage device that comprises multiple memory cells, writing data to a group of the memory cells by applying to the group of the memory cells up to a maximal number of programming pulses;

after applying less than the maximal number of programming pulses, evaluating a criterion that predicts whether or not the data will be written successfully within the maximal number of programming pulses, and

when the criterion predicts that writing the data will fail, performing a corrective operation.

12. The method according to claim 11, wherein evaluating the criterion comprises estimating a trend of a parameter measured over multiple programming pulses, wherein the parameter is indicative of a number of the memory cells in the group that have not yet reached their target levels.

13. The method according to claim 12, wherein the parameter comprises measurements of an electrical current consumed during respective programming pulses.

14. The method according to claim 12, wherein the parameter comprises numbers of memory cells that are inhibited from further programming after applying respective programming pulses.

15. The method according to claim 12, wherein estimating the trend comprises calculating differences between values of the parameter corresponding to different respective programming pulses, and wherein evaluating the criterion comprises predicting that writing the data will fail based on the differences.

16. The method according to claim 12, wherein estimating the trend comprises holding a reference parameter and calculating a distance metric between the parameter and the reference parameter, and wherein evaluating the criterion comprises predicting that writing the data will fail when the distance metric exceeds a given distance threshold.

17. The method according to claim 11, wherein evaluating the criterion comprises:

measuring an elapsed programming time since a starting time of writing the data; and

predicting that writing the data will fail when the elapsed programming time exceeds a given timeout limit.

18. The method to claim 17, and comprising determining the given timeout limit based on statistical properties of programming execution times.

19. The method according to claim 11, wherein the group of the memory cells comprises multiple subgroups that belong to different respective planes of the storage device, wherein writing the data comprises writing the data using a multi-plane programming operation that applies the programming pulses to the memory cells in the multiple subgroups in parallel, and wherein performing the corrective operation comprises applying a single-plane programming to at least one of the planes.

20. The method according to claim 19, wherein evaluating the criterion comprises:

measuring first and second parameters for respective first and second planes; and

predicting that writing the data will fail in at least one of the first and second planes based on both the first and second parameters.