Method of forming semiconductor structure with anti-punch through structure

• US 9,595,442 B2
• Filed: 02/17/2016
• Issued: 03/14/2017
• Est. Priority Date: 01/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wen, Tsung-Yao, Lai, Jui-Yao, Chiou, Yao-De, Yeong, Sai-Hooi, Chen, Yen-Ming
• Primary Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US15/046,046
• Publication Number:
  US 20160218007A1
• Time in Patent Office: 391 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for manufacturing a semiconductor structure is provided. The method includes implanting a first type of dopants in a first region and a second region of a substrate and implanting a second type of dopants in the second region of the substrate. The method includes forming a material layer over the first region and the second region of the substrate and patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure The method includes forming a gate structure across the first fin structure and the second fin structure.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

implanting a first type of dopants in a first region and a second region of a substrate;

implanting a second type of dopants in the second region of the substrate;

forming a material layer over the first region and the second region of the substrate;

patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure; and

forming a gate structure across the first fin structure and the second fin structure.

2. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the material layer is formed by an epitaxial (epi) process.

3. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the first fin structure comprises a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped material structure over the first type of anti-punch through structure, and the second fin structure comprises a second type of anti-punch through structure implanted with the second type of dopants and a second un-doped material structure formed over the second type of anti-punch through structure.

4. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein a doping concentration of the second type of dopants implanted in the second region is substantially twice of a doping concentration of the first type of dopants implanted in the second region.

5. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the material layer is a silicon layer.

6. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of patterning the material layer, the first region of the substrate, and the second region of the substrate further comprises:

forming a first polysilicon structure over the material layer over the first region of the substrate and a second polysilicon structure over the material over the second region of the substrate;

forming first spacers on sidewalls of the first polysilicon structure and second spacers on sidewalls of the second polysilicon structure;

removing the first polysilicon structure and the second polysilicon structure;

etching the material layer, the first region of the substrate, and the second region of the substrate to form the first fin structure and the second fin structure; and

removing the first spacers and the second spacers,

wherein the first spacers and the second spacers are used as masks when the material layer is etched.

7. The method for manufacturing a semiconductor structure as claimed in claim 1, further comprising:

annealing the first type of dopants and the second type of dopants before the material layer is formed, such that the first type of dopants and the second type of dopants are redistributed in the substrate but not in the material layer.

8. A method for manufacturing a semiconductor structure, comprising:

forming a strain relax buffer layer over a substrate;

implanting a first type of dopants in a first region of the strain relax buffer layer;

implanting a second type of dopants in the second region of the strain relax buffer layer;

forming a material layer over the first region and the second region of the strain relax buffer layer;

patterning the material layer, the first region of the strain relax buffer layer, and the second region of the strain relax buffer layer to form a first fin structure and a second fin structure; and

forming a gate structure across the first fin structure and the second fin structure.

9. The method for manufacturing a semiconductor structure as claimed in claim 8, further comprising:

annealing the first type of dopants and the second type of dopants before the material layer is formed, such that the first type of dopants and the second type of dopants are redistributed in the strain relax buffer layer but not in the material layer.

10. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein the first type of dopants and the second type of dopants are annealed at a temperature in a range from about 700°

C. to about 1000°

C.

11. The method for manufacturing a semiconductor structure as claimed in claim 8, wherein a doping concentration of the second type of dopants implanted in the second region is substantially twice of a doping concentration of the first type of dopants implanted in the second region.

12. The method for manufacturing a semiconductor structure as claimed in claim 8, wherein the material layer is formed by an epitaxial (epi) process.

13. The method for manufacturing a semiconductor structure as claimed in claim 8, wherein the first fin structure comprises a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped material structure over the first type of anti-punch through structure, and the second fin structure comprises a second type of anti-punch through structure implanted with both the first and the second types of dopants and a second un-doped material structure formed over the second type of anti-punch through structure.

14. A method for manufacturing a semiconductor structure, comprising:

implanting a first type of dopants in a first region of a substrate;

implanting a second type of dopants in a second region of the substrate;

forming a material layer over the first region and the second region of the substrate;

patterning the material layer, the first region of the substrate, and the second region of the substrate to form a first fin structure and a second fin structure; and

forming a gate structure across the first fin structure and the second fin structure.

15. The method for manufacturing a semiconductor structure as claimed in claim 14, further comprising:

annealing the first type of dopants and the second type of dopants before the material layer is formed, such that the first type of dopants and the second type of dopants are redistributed in the substrate but not in the material layer.

16. The method for manufacturing a semiconductor structure as claimed in claim 14, further comprising:

implanting the first type of dopants in the second region of the substrate.

17. The method for manufacturing a semiconductor structure as claimed in claim 16, wherein the first fin structure comprises a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped silicon structure over the first type of anti-punch through structure, and the second fin structure comprises a second type of anti-punch through structure implanted with both the first and the second types of dopants and a second un-doped silicon structure formed over the second type of anti-punch through structure.

18. The method for manufacturing a semiconductor structure as claimed in claim 16, wherein a doping concentration of the second type of dopants implanted in the second region is substantially twice of a doping concentration of the first type of dopants implanted in the second region.

19. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein the substrate comprise a strain relax buffer layer over the substrate, and the first type of dopants are implanted in a first region of the strain relax buffer layer and the second type of dopants are implanted in a second region of the strain relax buffer layer.

20. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein the first fin structure comprises a first type of anti-punch through structure implanted with the first type of dopants and a first un-doped silicon structure over the first type of anti-punch through structure, and the second fin structure comprises a second type of anti-punch through structure implanted with the second type of dopants and a second un-doped silicon structure formed over the second type of anti-punch through structure.