Semiconductor device including electromagnetic absorption and shielding

• US 9,595,454 B2
• Filed: 04/26/2012
• Issued: 03/14/2017
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Information Technology (Shanghai) Co., Ltd. (Western Digital Corporation)
• Inventors: Chiu, Chin-Tien, Huang, Dacheng, Bai, Ye, Qian, Kaiyou
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ahmed, Shahed
• Application Number:
  US14/348,828
• Publication Number:
  US 20140231973A1
• Time in Patent Office: 1,783 Days
• Field of Search: 257/422, 257/659, 257/660, 257/787, 257/790, 438/15, 438/112, 438/731, 438/25, 438/127
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06155 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06537 Electromagnetic shielding
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1438 : Flash memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 2201/0215 : Metallic fillers
• CPC Class Codes: H05K 2201/083 : Magnetic materials
• CPC Class Codes: H05K 3/3452 : Solder masks

Abstract

A semiconductor device is disclosed including material for absorbing EMI and/or RFI The device includes a substrate (202), one or more semiconductor die (224,225), and molding compound around the one or more semiconductor die (224,225). The material for absorbing EMI and/or RFI may be provided within or on a solder mask layer (210) on the substrate (202). The device may further include EMI/RFI-absorbing material around the molding compound and in contact with the EMI/RFI-absorbing material on the substrate to completely enclose the one or more semiconductor die in EMI/RFI-absorbing material.

Claims

1. A semiconductor device, comprising:

a substrate including a dielectric core, a conductive layer on the dielectric core, and a solder mask layer on the conductive layer, the substrate including a first absorbing material for absorbing at least one of EMI and RFI;

one or more semiconductor die affixed to the substrate;

an encapsulant covering the one or more semiconductor die; and

first and second continuous layers provided on the encapsulant, the first and second continuous layers being directly adjacent to each other, the first continuous layer including a second absorbing material for absorbing at least one of EMI and RFI, and the second continuous layer including a conductive material for shielding the semiconductor device against at least one of EMI and RFI.

2. The semiconductor device of claim 1, wherein the first absorbing material is provided as part of the solder mask.

3. The semiconductor device of claim 2, wherein the first absorbing material is mixed in as part of the solder mask.

4. The semiconductor device of claim 2, wherein the first absorbing material is provided as a layer on the solder mask prior to application of the solder mask to the substrate.

5. The semiconductor device of claim 1, wherein the first absorbing material is provided as a layer on the solder mask after application of the solder mask to the substrate.

6. The semiconductor device of claim 1, wherein the first absorbing material is provided as part of the dielectric core.

7. The semiconductor device of claim 1, wherein at least one of the first and second absorbing materials is ferrite.

8. The semiconductor device of claim 1, wherein at least one of the first and second absorbing materials is one of silicon carbide, carbon nanotube, magnesium dioxide, carbonyl iron powder, SENDUST, iron silicide, magnetic alloys and magnetic flakes and powders.

9. A semiconductor device, comprising:

a substrate;

a solder mask layer on the substrate, the solder mask layer including a first absorbing material for absorbing at least one of EMI and RFI;

one or more semiconductor die affixed and electrically connected to the substrate;

a molding compound encapsulating at least the one or more semiconductor die; and

first and second continuous layers provided on the molding compound, the first continuous layer including a second absorbing material for absorbing at least one of EMI and RFI, and the second continuous layer including a conductive material for shielding the semiconductor device against at least one of EMI and RFI.

10. The semiconductor device of claim 9, wherein the first absorbing material is mixed in as part of the solder mask.

11. The semiconductor device of claim 9, wherein the first absorbing material is provided as a layer on the solder mask prior to application of the solder mask to the substrate.

12. The semiconductor device of claim 9, further comprising a ground pin connected to a ground plane in the substrate and connected to the second layer.

13. The semiconductor device of claim 9, wherein the first and second absorbing materials are of the same composition.

14. The semiconductor device of claim 9, wherein the first layer of the second absorbing materials is provided on a top surface of the molding compound and on sides of the molding compound extending down and into contact with the solder mask layer on the substrate, the first and second absorbing materials completely encasing the one or more semiconductor die.

15. The semiconductor device of claim 9, wherein the first layer of the second absorbing material is provided on a top surface of the molding compound and not on sides of the molding compound that extend into contact with the solder mask layer.

16. The semiconductor device of claim 9, wherein the first layer of the second absorbing material is provided on the molding compound, and the second layer of the conductive material is provided on the first layer of absorbing material.

17. The semiconductor device of claim 9, wherein the second layer of the conductive material is provided on the molding compound, and the first layer of the second absorbing material is provided on the second layer of conducting material.