Method and structure of three dimensional CMOS transistors with hybrid crystal orientations

• US 9,595,479 B2
• Filed: 03/18/2014
• Issued: 03/14/2017
• Est. Priority Date: 07/08/2008
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao (Charles)
• Primary Examiner(s): Trinh, Michael
• Application Number:
  US14/218,633
• Publication Number:
  US 20150270180A1
• Time in Patent Office: 1,092 Days
• US Class Current: 1/1
• CPC Class Codes: A61B 5/14514 using means for aiding extraction of interstitial fluid, e.g. microneedles or suction
• CPC Class Codes: B81B 2201/025 Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
• CPC Class Codes: B81B 2201/055 Microneedles
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0054 integral with a semiconducting diaphragm
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03H 3/0073 Integration with other electronic structures

Abstract

A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.

Claims

1. A method for fabricating a three-dimensional integrated circuit device, the method comprising:

providing a first substrate having a first crystal orientation;

forming at least one or more PMOS devices overlying the first substrate;

forming a first dielectric layer overlying the one or more PMOS devices;

providing a second substrate having a second crystal orientation;

forming at least one or more NMOS devices overlying the second substrate;

forming a second dielectric layer overlying the one or more NMOS devices; and

coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate;

forming a third dielectric layer overlying the hybrid structure; and

forming a pressure sensing device overlying the third dielectric layer,

wherein forming the pressure sensing device comprising;

forming a diaphragm device having a first surface region facing and overlying the hybrid structure and a second surface region opposite the first surface region;

forming at least one or more folded spring devices spatially disposed within a vicinity of the first surface region of the diaphragm device, each of the folded spring devices being operably coupled to the first surface region of the diaphragm device;

forming two or more electrode devices operably coupled to the first surface region;

forming a first cavity region provided between the first surface region and the hybrid structure, the first cavity region being substantially sealed and maintaining a predetermined environment; and

forming a housing member provided overlying the second surface region of the diaphragm device to form a second cavity region between the housing member and the diaphragm device, the housing member comprising one or more fluid openings to allow fluid to move between the second cavity and a region outside of the housing member.

2. The method of claim 1 wherein the first crystal orientation comprises a (110) crystal orientation or a (111) crystal orientation.

3. The method of claim 1 wherein the second crystal orientation comprises a (100) crystal orientation.

4. The method of claim 1 wherein the coupling of the first and second dielectric layer comprises a covalent, eutectic, glass frit, SOG, thermal compression, or fusion bonding process.

5. The method of claim 1 further comprising forming one or more trench isolation (STI) oxides formed to isolate adjacent transistors.

6. The method of claim 1 further comprising thinning the first substrate via a grinding, polishing, etching, or cleaving process.

7. The method of claim 1 wherein the forming of the one or more PMOS transistors comprises an implanting process in a (111) silicon substrate.

8. The method of claim 7 wherein the implanting process comprises implanting H₂, He, or Ar in a desired depth in the silicon substrate.

9. The method of claim 1 further comprising forming one or more vertical interconnects within one or more portions of the hybrid structure.

10. A method for forming a three-dimensional integrated circuit device comprising:

forming a first substrate having a first crystal orientation and including;

at least one or more PMOS device thereon; and

a first dielectric layer overlying the one or more PMOS devices;

forming a second substrate having a second crystal orientation, and including;

at least one or more NMOS devices thereon; and

a second dielectric layer overlying the one or more NMOS devices;

coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate; and

forming a pressure sensing device overlying the hybrid structure,

wherein forming the pressure sensing device comprising;

forming a diaphragm device having at least a first diaphragm surface region facing the hybrid structure and a second diaphragm surface region opposite the first surface region;

forming one or more spring devices spatially disposed within a vicinity of the first diaphragm surface region of the diaphragm device, each of the spring devices being operably coupled to the first diaphragm surface region of the diaphragm device;

forming two or more electrode devices operably coupled to the first diaphragm surface region;

forming at least one fluid channel formed between the two or more electrode devices, at least one of the fluid channels being in communication with the first diaphragm surface region of the diaphragm device; and

forming a housing member provided overlying the diaphragm device to form a cavity region between the housing member and the diaphragm device, the housing member comprising one or more first fluid openings to allow fluid to move between the cavity and a first region outside of the housing member, the one or more fluid openings being in communication with the second diaphragm surface region of the diaphragm.

11. The method of claim 10 wherein the first crystal orientation comprises a (110) crystal orientation or a (111) crystal orientation.

12. The method of claim 10 wherein the second crystal orientation comprises a (100) crystal orientation.

13. The method of claim 10 wherein the coupling of the first and second dielectric layer comprises a covalent, eutectic, glass frit, SOG, thermal compression, or fusion bonding process.

14. The method of claim 10 further comprising forming one or more trench isolation (STI) oxides formed to isolate adjacent transistors.

15. The method of claim 10 further comprising thinning the first substrate via a grinding, polishing, etching, or cleaving process.

16. The method of claim 10 wherein the forming of the one or more PMOS transistors comprises an implanting process in a (111) silicon substrate.

17. The method of claim 10 wherein the implanting process comprises implanting H₂, He, or Ar in a desired depth in the silicon substrate.

18. The method of claim 10 wherein further comprising forming one or more vertical interconnects within one or more portions of the hybrid structure.