Power converter

• US 9,595,484 B2
• Filed: 02/26/2016
• Issued: 03/14/2017
• Est. Priority Date: 02/27/2015
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Ohno, Hirotaka
• Primary Examiner(s): Zhang, Jue
• Application Number:
  US15/055,211
• Publication Number:
  US 20160254206A1
• Time in Patent Office: 382 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/051 another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/40 Mountings or securing means for detachable cooling or heating arrangements heating H01L23/345; fixed by friction, plugs or springs
• CPC Class Codes: H01L 23/4012 for stacked arrangements of a plurality of semiconductor devices assemblies per se H01L25/00
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 25/117 Stacked arrangements of devices
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

In a power converter, a plurality of semiconductor devices and a plurality of cooling plates are stacked. The plurality of semiconductor devices includes a first-first sealed semiconductor device, a second-first sealed semiconductor device, and a plurality of second sealed semiconductor devices. The first-first sealed semiconductor device has a first high potential side terminal, and a first low potential side terminal. The second-first sealed semiconductor device has a second high potential side terminal, and a second low potential side terminal. When viewed along a stacking direction, the first high potential side terminal is disposed to overlap with the second low potential side terminal.

Claims

1. A power converter comprising:

a plurality of semiconductor devices; and

a plurality of cooling plates,

wherein

the plurality of semiconductor devices are stacked alternately with the plurality of cooling plates, each of the semiconductor devices being in close contact with the corresponding adjacent cooling plate,

the plurality of semiconductor devices includes a first-first sealed semiconductor device, a second-first sealed semiconductor device, and a second sealed semiconductor device,

each of the first-first sealed semiconductor device and the second-first sealed semiconductor device comprises a first semiconductor structure which is sealed with first resin, and the first semiconductor structure includes a first transistor and a first diode connected in parallel with the first transistor,

the first-first sealed semiconductor device includes;

a first high potential side terminal connected to a cathode of the first diode of the first-first sealed semiconductor device, a first portion of the first high potential side terminal being outside of the first resin; and

a first low potential side terminal connected to an anode of the first diode of the first-first sealed semiconductor device, a second portion of the first low potential side terminal being outside of the first resin,

the second-first sealed semiconductor device includes;

a second high potential side terminal connected to a cathode of the first diode of the second-first sealed semiconductor device, a third portion of the second high potential side terminal being outside of the first resin; and

a second low potential side terminal connected to an anode of the first diode of the second-first sealed semiconductor device, a fourth portion of the second low potential side terminal being outside of the first resin,

the second sealed semiconductor device comprises a plurality of second semiconductor structures,

each of the second semiconductor structures is sealed with second resin and includes a second transistor and a second diode connected in parallel with the second transistor,

at least two of the second transistors included in the plurality of second semiconductor structures are connected in series,

the first low potential side terminal of the first-first sealed semiconductor device is connected with the second high potential side terminal of the second-first sealed semiconductor device, and

when viewed along a stacking direction of the plurality of semiconductor devices and the plurality of cooling plates, the first portion of the first high potential side terminal of the first-first sealed semiconductor device that is outside of the first resin is disposed to overlap with the fourth portion of the second low potential side terminal of the second-first sealed semiconductor device that is outside of the first resin.

2. The power converter according to claim 1, wherein the second transistor and the second diode included in each of the second semiconductor structures are incorporated in a semiconductor substrate.

3. The power converter according to claim 1, wherein when viewed along the stacking direction, the second portion of the first low potential side terminal that is outside of the first resin is disposed to overlap with the third portion of the second high potential side terminal that is outside of the first resin.

4. The power converter according to claim 1, further comprising a converter circuit and an inverter circuit,

wherein the converter circuit is formed by the first-first sealed semiconductor device, the second-first sealed semiconductor device, and a reactor which is connected between a power supply and a conductor connecting the first low potential side terminal and the second high potential side terminal,

the inverter circuit is formed by a plurality of second sealed semiconductor devices, and

one end of the second transistors connected in series is connected to the first high potential side terminal and the other end is connected to the second low potential side terminal in each of the second sealed semiconductor devices.

5. The power converter according to claim 4, further comprising a third-first sealed semiconductor device,

wherein the converter circuit is formed by the first-first sealed semiconductor device, the second-first sealed semiconductor device, the third-first sealed semiconductor device and the reactor, and

the third-first sealed semiconductor device comprises a first semiconductor structure which is sealed with first resin, and the first semiconductor structure of the third-first semiconductor device includes a first transistor and a first diode connected in parallel with the first transistor.

6. The power converter according to claim 5, wherein a third high potential side terminal of the third-first sealed semiconductor device is connected to the first low potential side terminal of the first-first sealed semiconductor device.

7. The power converter according to claim 6, wherein

the first-first sealed semiconductor device and the third-first sealed semiconductor device are stacked via one of the cooling plates, and

when viewed along the stacking direction, the first portion of the first high potential side terminal that is outside of the first resin is disposed to overlap with a portion of a third low potential side terminal that is outside of the first resin.

8. The power converter according to claim 5, wherein a third low potential side terminal of the third-first sealed semiconductor device is connected to the second high potential side terminal.

9. The power converter according to claim 8, wherein

the first-first sealed semiconductor device and the third-first sealed semiconductor device are stacked via one of the cooling plates, and

when viewed along the stacking direction, the first portion of the first high potential side terminal that is outside of the first resin is disposed to overlap with a portion of a third high potential side terminal of the third-first sealed semiconductor device that is outside of the first resin.

10. The power converter according to claim 1, wherein

a first semiconductor element in which the first semiconductor structure is incorporated and a second semiconductor element in which a third semiconductor structure is incorporated are sealed by the first resin,

the third semiconductor structure includes a third transistor and a third diode connected in parallel with the third transistor, and

the first transistor and the third transistor are connected in parallel.