Device manufacture and packaging method thereof

• US 9,595,492 B2
• Filed: 03/16/2015
• Issued: 03/14/2017
• Est. Priority Date: 03/16/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chien-Hsuan
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US14/658,540
• Publication Number:
  US 20160276266A1
• Time in Patent Office: 729 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00

Abstract

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

Claims

1. A method of manufacturing a semiconductive device, comprising:

forming a top dielectric layer over a bottom dielectric layer having a recess;

forming a photosensitive layer over the top dielectric layer; and

exposing a first portion and a second portion of the photosensitive layer,

wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess,

wherein the method of exposing the first portion of the photosensitive layer is simultaneously performed with the method of exposing the second portion of the photosensitive layer.

20. The method of claim 1, further comprising forming a conductive material inside the recess.

2. A method of manufacturing a semiconductive device, comprising:

forming a top dielectric layer over a bottom dielectric layer having a recess;

forming a photosensitive layer over the top dielectric layer; and

exposing a first portion and a second portion of the photosensitive layer,

wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess, and

wherein the method of exposing the first portion of the photosensitive layer is subsequently followed by the method of exposing the second portion of the photosensitive layer.

3. The method of claim 2, further comprising forming a conductive material inside the recess.

4. The method of claim 3, further comprising forming a conductive layer over the recess, wherein a thickness of the conductive layer is more than about 2 micrometers.

5. A method of manufacturing a semiconductive device, comprising:

forming a top dielectric layer over a bottom dielectric layer having a recess;

forming a photosensitive layer over the top dielectric layer;

exposing a first portion and a second portion of the photosensitive layer, and

removing a portion of the top dielectric layer under the first portion and the second portion of the photosensitive layer,

wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess.

6. A method of manufacturing a semiconductive device, comprising:

forming a top dielectric layer over a bottom dielectric layer having a recess, the top dielectric layer having a thickens more than about 2 micrometers; and

patterning the top dielectric layer from a first portion and a second portion of a photosensitive layer over the top dielectric layer,

wherein the second portion protruding from the first portion in a lateral direction, and the second portion substantially overlaps with the recess.

7. The method of claim 6, wherein the patterning the top dielectric layer comprises patterning the first portion and the second portion simultaneously.

8. The method of claim 7, wherein the patterning the first portion and the second portion simultaneously comprises:

exposing the first portion and the second portion of the photosensitive layer in one operation.

9. The method of claim 7, wherein the patterning the first portion and the second portion simultaneously comprises removing a portion of the top dielectric layer.

10. The method of claim 6, wherein the patterning the top dielectric layer comprises patterning the first portion and the second portion sequentially.

11. The method of claim 10, wherein the patterning the first portion and the second portion sequentially comprises:

exposing a first portion of the photosensitive layer; and

exposing a second portion of the photosensitive layer after the exposing the first portion of the photosensitive layer.

12. The method of claim 10, wherein the patterning the first portion and the second portion sequentially comprises:

removing a portion of the top dielectric layer according to the first portion of the photosensitive layer; and

removing a portion of the top dielectric layer according to the second portion of the photosensitive layer after removing the portion of the top dielectric layer according to the first portion.

13. A method of manufacturing a semiconductive device, comprising:

forming a first conductive layer;

forming a via structure on top of the first conductive layer, the via structure comprising a lateral side;

forming a second conductive layer over the via structure, the second conductive layer comprising a lateral boundary of a first region connected to the lateral side of the via structure such that a first portion of the lateral boundary is aligned vertically with the lateral side of the via structure.

14. The method of claim 13, further comprising forming a protective layer over the first conductive layer and surrounding the via structure in proximity to the first conductive layer.

15. The method of claim 14, wherein the forming the protective layer comprises forming a nitride layer.

16. The method of claim 13, wherein the first portion of the lateral boundary comprises a protruding portion.

17. The method of claim 13, wherein the forming the second conductive layer further comprises forming a second region distanced from the first portion of the lateral boundary by a predetermined value.

18. The method of claim 13, wherein the forming the via structure comprises filling conductive material similar to that of the second conductive layer into a via opening.

19. The method of claim 13, wherein the lateral side of the via structure is formed to be in contact with the first conductive layer.