Microelectronic packages and assemblies with improved flyby signaling operation

• US 9,595,511 B1
• Filed: 05/12/2016
• Issued: 03/14/2017
• Est. Priority Date: 05/12/2016
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Haba, Belgacem, Sun, Zhuowen, Delacruz, Javier A.
• Primary Examiner(s): Ho, Tu-Tu
• Application Number:
  US15/153,367
• Time in Patent Office: 306 Days
• Field of Search: 257/686
• US Class Current: 1/1
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24175 the item being metallic
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00

Abstract

A microelectronic unit includes microelectronic elements having memory storage arrays. First terminals and second terminals at a surface of the microelectronic unit are configured for connection with corresponding first and second sets of circuit panel contacts which are coupled with conductors of a common signaling bus on the circuit panel. Front surfaces of first and second microelectronic elements define a plurality of first planes at a substantial angle to a second plane defined by the major surface of the circuit panel. Each of a plurality of delay elements within the microelectronic unit is electrically coupled with a signaling path of the common signaling bus between one of the first terminals and a corresponding second terminal. In such way, the delay elements may reduce adverse effects of additive signal energy reflected from the microelectronic packages back towards the common signaling bus.

Claims

1. A microelectronic assembly, comprising:

a circuit panel having panel contacts at a major surface thereof, and electrically conductive elements configured to conduct signals of a common signaling bus, the electrically conductive elements coupled with respective sets of the panel contacts at respective first and second connection regions at the major surface; and

a microelectronic unit comprising a plurality of microelectronic packages, each package having a surface and a plurality of terminals at the surface, the terminals of the respective package coupled with the respective set of panel contacts,

each package comprising a microelectronic element having a front surface and element contacts at the front surface, each microelectronic element including a memory storage array, wherein the front surface of the microelectronic element is disposed at a substantial angle relative to a plane defined by the major surface of the circuit panel; and

the at least one microelectronic unit further comprising a plurality of delay elements thereon, each delay element electrically coupled with a signaling path of the common signaling bus extending on the microelectronic unit between a first terminal of a first package coupled to a panel contact at the first connection region, and a second terminal of the microelectronic unit coupled to a panel contact at the second connection region, the signaling path electrically coupled to the microelectronic element of the first package between the first terminal and the second terminal, whereby each delay element is configured to increase a total electrical length along the signaling path between the first connection region and a connection region at which a package adjacent to the first package is electrically coupled.

2. The microelectronic assembly of claim 1, wherein a pitch between the first planes defined by the front surfaces of adjacent microelectronic packages is smaller than a width dimension of the microelectronic packages in a direction parallel to the first planes.

3. The microelectronic assembly of claim 1, wherein the delay elements comprise electrical conductors extending in directions of a plane.

4. The microelectronic assembly of claim 3, wherein the electrical conductors extend along at least one of the front or rear surfaces of at least one of the plurality of microelectronic elements.

5. The microelectronic assembly of claim 4, wherein the electrical conductors extend along the rear surface of the microelectronic element.

6. The microelectronic assembly of claim 5, wherein the electrical conductors extend on the first package.

7. The microelectronic assembly of claim 1, wherein the delay elements comprise electrical conductors extending in directions transverse to the first planes.

8. The microelectronic assembly of claim 3, wherein the electrical conductors are supported on a supplementary element and are electrically coupled to the second connection region.

9. The microelectronic assembly of claim 8, wherein the supplementary element is disposed between adjacent ones of the microelectronic packages.

10. The microelectronic assembly of claim 8, wherein the supplementary element is disposed between adjacent ones of the microelectronic elements within one of the at least one microelectronic package.

11. The microelectronic assembly of claim 8, wherein the microelectronic unit includes a plurality of microelectronic packages, wherein the supplementary element is disposed between first and second adjacent microelectronic packages of the plurality of microelectronic packages.

12. The microelectronic assembly of claim 3, wherein the plurality of microelectronic elements includes a set of microelectronic elements in which the set includes through vias extending in directions transverse to said set of planes, wherein at least some of the plurality of microelectronic elements of the set have element contacts electrically coupled to one another and to the delay elements by way of the through vias.

13. The microelectronic assembly of claim 8, wherein the supplementary element has a surface extending parallel to said second plane, wherein the electrical conductors extend in at least one direction substantially parallel to the second plane.

14. A microelectronic unit, comprising:

a plurality of microelectronic elements each having a front surface, and element contacts at the front surface, each microelectronic element including a memory storage array;

first terminals and second terminals at an exterior surface of the microelectronic unit, the first terminals and the second terminals configured for connection with corresponding first and second sets of panel contacts at first and second connection regions of a circuit panel, respectively, the first and second sets of panel contacts coupled with the conductors of a common signaling bus extending along the circuit panel, wherein the front surfaces of the first and second microelectronic elements define a plurality of first planes which are non-parallel with a second plane defined by the major surface of the circuit panel; and

a plurality of delay elements on the microelectronic unit each delay element electrically coupled with a signaling path of the common signaling bus between one of the first terminals and a corresponding second terminal of the plurality of second terminals, the signaling path coupled to a contact of at least one microelectronic element between the first terminal and the corresponding second terminal, each delay element configured to increase a total electrical length along the signaling path between the first terminal and the corresponding second terminal.

15. The microelectronic unit of claim 14, wherein a pitch between the front surfaces of adjacent microelectronic elements of the plurality of microelectronic elements is smaller than a width dimension of a microelectronic package in a direction parallel to the first planes.

16. The microelectronic unit of claim 14, wherein the delay elements comprise electrical conductors extending substantially in directions of a plane parallel to the first planes.

17. The microelectronic unit of claim 16, wherein the microelectronic elements have rear surfaces remote from their respective front surfaces, and the electrical conductors extend in directions of a plane parallel to the rear surface of at least one of the plurality of microelectronic elements.

18. The microelectronic unit of claim 14, wherein the delay elements comprise electrical conductors supported on a supplementary element.

19. The microelectronic unit of claim 18, wherein the microelectronic elements are packaged in a plurality of microelectronic packages of the microelectronic unit, wherein the supplementary element is disposed between adjacent ones of the microelectronic packages.

20. The microelectronic unit of claim 18, wherein the microelectronic elements are packaged in at least one microelectronic package, wherein the supplementary element is disposed between adjacent ones of a plurality of the microelectronic elements within a microelectronic package of the microelectronic unit.

21. The microelectronic unit of claim 14, wherein the plurality of microelectronic elements includes a set of microelectronic elements in which the set includes through vias extending in directions transverse to said first planes, wherein at least some of the plurality of microelectronic elements of the set have element contacts electrically coupled to one another and to the delay elements by way of the through vias.

22. The microelectronic unit of claim 18, wherein the delay elements comprise electrical conductors extending in directions transverse to the first planes.

23. The microelectronic unit of claim 18, wherein the delay elements comprise at least one set of second electrical conductors extending on the microelectronic unit in directions substantially parallel to the major surface of the circuit panel, wherein the first connection region and the second connection region are electrically coupled through the at least one set of second conductors.