Field effect transistor and method of fabricating the same

• US 9,595,610 B2
• Filed: 05/28/2015
• Issued: 03/14/2017
• Est. Priority Date: 07/07/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kwon, TaeYong, Maeda, Shigenobu, Seo, David, Lee, Jae-Hwan
• Primary Examiner(s): YEUNG LOPEZ, FEIFEI
• Application Number:
  US14/723,673
• Publication Number:
  US 20160005864A1
• Time in Patent Office: 656 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

Claims

1. A field effect transistor, comprising:

a semiconductor substrate;

an active pattern protruding from the semiconductor substrate;

a buffer pattern interposed between the active pattern and the semiconductor substrate;

a gate electrode crossing and partially covering top and side surfaces of the active pattern;

a gate insulating layer interposed between the gate electrode and the active pattern; and

source and drain patterns spaced apart from the buffer pattern, each of the source and drain patterns comprising an epitaxial layer and an insertion portion inserted into the active pattern at a corresponding one of both sides of the gate electrode,

wherein the active pattern has a lattice constant different from that of the buffer pattern, so that the active pattern is strained by the buffer pattern, wherein the source and drain patterns have a lattice constant different from that of the active pattern,

wherein the active pattern is in contact with the buffer pattern, and

wherein the insertion portion of the source and drain patterns has a thickness ranging from about ⅓

to about ⅔

the thickness of the active pattern.

2. The field effect transistor of claim 1, wherein the source and drain patterns have top surfaces positioned at a higher level than a top surface of the active pattern.

3. The field effect transistor of claim 1, wherein the active pattern is of a p-type, the source and drain patterns are of an n-type, and the buffer pattern has a lattice constant larger than that of the active pattern.

4. The field effect transistor of claim 3, wherein the source and drain patterns have a lattice constant smaller than that of the active pattern.

5. The field effect transistor of claim 1, wherein the active pattern is of an n-type, the source and drain patterns are of a p-type, and the buffer pattern has a lattice constant smaller than that of the active pattern.

6. The field effect transistor of claim 5, wherein the source and drain patterns have a lattice constant larger than that of the active pattern.

7. The field effect transistor of claim 1, wherein the source and drain patterns have bottom surfaces positioned at a higher level than a lowermost surface of the gate electrode.

8. A field effect transistor, comprising:

a semiconductor substrate;

an active pattern protruding from the semiconductor substrate;

a buffer pattern interposed between the active pattern and the semiconductor substrate, the active pattern and buffer layer having a strain-inducing mismatch in lattice constants;

a gate electrode crossing and partially covering top and side surfaces of the active pattern;

a gate insulating layer interposed between the gate electrode and the active pattern;

source and drain regions formed in portions of the active pattern at both sides of the gate electrode and doped with impurities; and

source and drain patterns provided on the source and drain regions, respectively, each of the source and drain patterns including an epitaxial layer, wherein bottom surfaces of the source and drain patterns are above a top surface of the buffer layer, wherein the active pattern is not recessed.

9. The field effect transistor of claim 8, wherein the strain is a compressive strain.

10. The field effect transistor of claim 8, wherein the strain is a tensile strain.

11. An electronic device including the field effect transistor of claim 8.