Double-masking technique for increasing fabrication yield in superconducting electronics
First Claim
1. A method of forming a superconducting integrated circuit, comprising:
- forming an adhesion layer formed directly on top of an upper superconductor layer of a Josephson junction trilayer comprising the upper superconductor, an insulating layer, and a lower superconductor;
forming and patterning a resist layer directly on top of the adhesion layer, to expose portions of the adhesion layer through the resist layer and form resist layer edges;
exposing portions of the insulating layer corresponding to patterning of the resist layer by etching through the exposed portions of the adhesion layer and through the upper superconductor layer;
anodizing portions of the lower superconducting layer underlying the exposed portions of the insulating layer in an anodization solution, to selectively form circuit patterns comprising Josephson junction circuit elements under unexposed portions of the adhesion layer, the anodized portions of the lower superconductor layer being volumetrically expanded with respect to the non-anodized portions of the lower superconductor layer to form a layer of anodized superconductor on exposed sidewalls of the upper superconductor and insulating layer, inducing stresses on the adjacent resist layer edges; and
preventing peeling of the resist layer and leeching of etching solution under the resist layer subject to the anodization-induced stresses on the adjacent resist layer edges, by adhesion of the adhesion layer to the resist layer,wherein in an absence of the adhesion layer with direct deposition of the resist layer on the upper superconductor layer, the resist layer would peel from the upper superconductor layer and the anodization solution would leech under the resist layer, causing fabrication defects, andwherein the adhesion layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects of the adhesion layer during the anodizing.
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Accused Products
Abstract
An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
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Citations
20 Claims
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1. A method of forming a superconducting integrated circuit, comprising:
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forming an adhesion layer formed directly on top of an upper superconductor layer of a Josephson junction trilayer comprising the upper superconductor, an insulating layer, and a lower superconductor; forming and patterning a resist layer directly on top of the adhesion layer, to expose portions of the adhesion layer through the resist layer and form resist layer edges; exposing portions of the insulating layer corresponding to patterning of the resist layer by etching through the exposed portions of the adhesion layer and through the upper superconductor layer; anodizing portions of the lower superconducting layer underlying the exposed portions of the insulating layer in an anodization solution, to selectively form circuit patterns comprising Josephson junction circuit elements under unexposed portions of the adhesion layer, the anodized portions of the lower superconductor layer being volumetrically expanded with respect to the non-anodized portions of the lower superconductor layer to form a layer of anodized superconductor on exposed sidewalls of the upper superconductor and insulating layer, inducing stresses on the adjacent resist layer edges; and preventing peeling of the resist layer and leeching of etching solution under the resist layer subject to the anodization-induced stresses on the adjacent resist layer edges, by adhesion of the adhesion layer to the resist layer, wherein in an absence of the adhesion layer with direct deposition of the resist layer on the upper superconductor layer, the resist layer would peel from the upper superconductor layer and the anodization solution would leech under the resist layer, causing fabrication defects, and wherein the adhesion layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects of the adhesion layer during the anodizing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 16, 17)
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11. A method of forming an integrated circuit having Josephson junctions, comprising:
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forming a Josephson junction trilayer comprising an upper superconductor, an insulating layer, and a lower superconductor on a substrate; depositing an adhesion layer directly on top of the upper superconductor; forming a resist layer directly on top of the adhesion layer; patterning and developing the resist layer, to expose portions of the adhesion layer through the resist layer; etching the exposed portions of the adhesion layer through the upper superconductor to expose the insulating layer; selectively anodizing portions of the lower superconductor under the exposed portions of the insulating layer, to selectively form Josephson junction circuit elements under remaining portions of the adhesion layer and the resist layer, wherein the anodized portions of the lower superconductor increase in volume with respect to the non-anodized portions under remaining portions of the resist layer and grow beyond the insulating layer to form a layer of anodized lower superconductor on an exposed sidewall of the upper superconductor, the increase in volume inducing stresses on the resist layer at a patterned edge of the resist layer, the adhesion layer having sufficient adhesion to the resist layer and to the upper superconductor to maintain adhesion when subject to the stresses; and removing at least a portion of the exposed portions of the insulating layer and the anodized portions of the lower superconductor to expose the lower superconductor, wherein the adhesion layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects during the anodizing. - View Dependent Claims (12, 13, 14)
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18. A method for fabrication of an integrated circuit having Josephson junctions, comprising the steps of:
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providing a substrate, having a Josephson junction trilayer thereon comprising a lower superconducting layer, an insulating layer, and an upper superconducting layer, the upper superconducting layer being directly covered by an intermediate layer comprising a dielectric having a thickness of at least 5 nm, which in turn is directly covered by a resist layer; selectively patterning portions of the resist layer in dependence on an irradiation pattern, and developing the pattered portions of the resist layer to expose portions of the intermediate layer; etching the exposed portions of the intermediate layer and underlying portions of the upper superconducting layer, substantially without removing remaining portions of the resist layer, to expose the insulating layer, to thereby form a bilayer anodization mask comprising the resist layer and the intermediate layer; and anodizing the exposed insulating layer and underlying lower superconducting layer through the bilayer mask cause a volumetric increase in at least the lower superconducting layer, such that anodized superconductor of the lower superconductor layer volumetrically expands above the intermediate layer, and stresses are induced in the resist layer, to selectively form Josephson junction circuit elements comprising intact portions of the Josephson junction trilayer protected by the bilayer mask, wherein the resist layer remains strongly adherent to the intermediate layer, and the intermediate layer remains strongly adherent to the upper superconducting layer, substantially without peeling, wherein the intermediate layer is a thin layer subject to pinhole defects, and wherein the resist layer covers the pinhole defects during the anodizing. - View Dependent Claims (19, 20)
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Specification