STT-MRAM cell structures

• US 9,595,664 B2
• Filed: 01/13/2015
• Issued: 03/14/2017
• Est. Priority Date: 01/09/2009
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun, Sandhu, Gurtej
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/595,955
• Publication Number:
  US 20150125966A1
• Time in Patent Office: 791 Days
• Field of Search: 438/3
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H01L 29/66007 Multistep manufacturing processes
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Claims

1. A method of fabricating a memory cell comprising:

etching a dielectric layer to form a recess exposing a portion of a pinned layer; and

depositing conductive nonmagnetic material in the recess in contact with the portion of the pinned layer,

wherein etching the dielectric layer to form the recess comprises removing a portion of the dielectric layer at an outermost edge of the memory cell.

2. The method, as set forth in claim 1, wherein etching the dielectric layer comprises dry etching or isotropic etching to expose the portion of the pinned layer.

3. The method, as set forth in claim 1, wherein etching the dielectric layer comprises etching a trench, etching a via, or etching a mesa to expose the portion of the pinned layer.

4. The method, as set forth in claim 1, wherein depositing the conductive nonmagnetic material comprises depositing via physical vapor deposition, chemical vapor deposition, conformal chemical vapor deposition, or electroplating.

5. The method, as set forth in claim 1, wherein depositing the conductive nonmagnetic material comprises forming a spacer on a sidewall of the recess in the dielectric layer.

6. The method, as set forth in claim 5, comprising depositing a dielectric material into the recess.

7. A method of fabricating a memory cell comprising:

etching a dielectric layer to form a recess exposing a portion of a pinned layer;

depositing nonmagnetic material in the recess in contact with the portion of the pinned layer; and

depositing dielectric material in the recess such that the dielectric material, the dielectric layer and the nonmagnetic material collectively form a single layer.

8. The method, as set forth in claim 7, comprising

planarizing the single layer;

depositing a free layer on the single layer, wherein the free layer is in contact with the nonmagnetic material; and

depositing an electrode layer on the free layer.

9. A method of fabricating a memory cell comprising:

etching a dielectric layer to form a recess exposing a portion of a pinned layer; and

depositing nonmagnetic material in the recess in contact with the portion of the pinned layer, wherein;

etching the dielectric layer to form a recess exposes a portion of a free layer; and

depositing the nonmagnetic material in the recess comprises depositing the nonmagnetic material by conformal vapor deposition in contact with the portion of the free layer.

10. The method, as set forth in claim 9, comprising:

removing a first portion of nonmagnetic material, wherein a second portion of nonmagnetic material is in the recess and in contact with the portion of the pinned layer and the portion of the free layer.

11. The method, as set forth in claim 10, wherein removing the first portion of nonmagnetic material comprises isotropic etching, or any other etching suitable for removing the first portion of nonmagnetic material.

12. A method of fabricating a memory cell comprising:

etching a dielectric layer to form a recess exposing a portion of a pinned layer;

depositing nonmagnetic material in the recess in contact with the portion of the pinned layer;

depositing dielectric material to surround the sides of the nonmagnetic material, wherein a layer of dielectric and nonmagnetic material is formed;

planarizing the layer of dielectric and nonmagnetic material to expose the nonmagnetic material; and

depositing a free layer on the layer of dielectric and nonmagnetic material, wherein the free layer is in contact with the nonmagnetic material.

13. A method of fabricating a memory cell comprising:

forming a recess in a dielectric layer to expose a portion of a pinned layer; and

depositing conductive nonmagnetic material in the recess in contact with the portion of the pinned layer,

wherein forming the recess in the dielectric layer comprises forming a recess in the dielectric layer to expose a portion of a free layer overlying the dielectric layer.

14. The method, as set forth in claim 13, wherein forming the recess comprises removing a portion of the dielectric layer at an outer edge of the memory cell.

15. The method, as set forth in claim 13, wherein forming the recess in the dielectric layer comprises forming a recess in a dielectric layer to expose a portion of a pinned layer underlying the dielectric layer.

16. The method, as set forth in claim 13, comprising forming a free layer on a surface of the dielectric layer opposite the pinned layer.

17. A method of fabricating a memory cell comprising:

forming a recess in a dielectric layer to expose a portion of a pinned layer; and

depositing nonmagnetic material in the recess in contact with the portion of the pinned layer,

wherein forming the recess comprises removing an outer portion of the dielectric layer such that an annular void around the dielectric layer is formed.

18. The method, as set forth in claim 17, wherein depositing the nonmagnetic material comprises filling the annular void.

19. A method of fabricating a memory cell comprising:

forming a recess in a dielectric layer to expose a portion of a pinned layer; and

depositing nonmagnetic material in the recess in contact with the portion of the pinned layer,

wherein forming the recess comprises removing a portion of the dielectric at a center of the memory cell.

20. A method of fabricating a memory cell comprising:

forming a pinned ferromagnetic layer;

forming a dielectric layer on the pinned ferromagnetic layer;

forming a free ferromagnetic layer on the dielectric layer;

forming a recess in the dielectric layer; and

forming a conductive nonmagnetic material in the recess,

wherein forming the nonmagnetic material in the recess comprises disposing the nonmagnetic material in the recess, wherein the recess is formed about a perimeter of the dielectric material such that dielectric material is surrounded about a perimeter of the nonmagnetic material.

21. The method, as set forth in claim 20, comprising forming an antiferromagnetic layer, and wherein the forming of the pinned ferromagnetic layer is performed such that the antiferromagnetic layer is beneath the pinned ferromagnetic layer.

22. The method, as set forth in claim 20, comprising forming an electrode layer on the free ferromagnetic layer.

23. The method, as set forth in claim 20, wherein forming the conductive nonmagnetic material in the recess comprises forming a spacer on sidewalls of the recess.

24. A method of fabricating a memory cell comprising:

forming a pinned ferromagnetic layer;

forming a dielectric layer on the pinned ferromagnetic layer;

forming a free ferromagnetic layer on the dielectric layer;

forming a recess in the dielectric layer; and

forming a nonmagnetic material in the recess,

wherein forming the nonmagnetic material in the recess comprises disposing the nonmagnetic material in the recess, wherein the recess is formed in a center of the dielectric material such that a perimeter of the nonmagnetic material is surrounded by the dielectric material.