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STT-MRAM cell structures

  • US 9,595,664 B2
  • Filed: 01/13/2015
  • Issued: 03/14/2017
  • Est. Priority Date: 01/09/2009
  • Status: Active Grant
First Claim
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1. A method of fabricating a memory cell comprising:

  • etching a dielectric layer to form a recess exposing a portion of a pinned layer; and

    depositing conductive nonmagnetic material in the recess in contact with the portion of the pinned layer,wherein etching the dielectric layer to form the recess comprises removing a portion of the dielectric layer at an outermost edge of the memory cell.

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