Radio-frequency switches having gate bias and frequency-tuned body bias

• US 9,595,951 B2
• Filed: 08/29/2014
• Issued: 03/14/2017
• Est. Priority Date: 07/07/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Sprinkle, Steven Christopher, Altunkilic, Fikret, Cebi, Haki
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): SKIBINSKI, THOMAS S
• Application Number:
  US14/474,050
• Publication Number:
  US 20150022256A1
• Time in Patent Office: 928 Days
• Field of Search: 327/534, 327/535, 327/537, 327/384, 327/427, 327/434, 327/437, 327/379, 455/78
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

Claims

1. A radio-frequency (RF) switch comprising:

a plurality of field-effect transistors (FETs) disposed between a first node and a second node, each of the plurality of FETs having a respective source, drain, gate and body, the plurality of FETs including a first FET connected in series with a second FET;

a coupling circuit that connects the body of each of the plurality of FETs to the gate of each of the plurality of FETs, the coupling circuit including a first circuit coupled in series to a resistance, the first circuit including a capacitance and a diode, the coupling circuit configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, the approximately closed circuit allowing removal of surface charge from the body;

a bias circuit that connects the gate of each of the plurality of FETs to a gate bias voltage, the bias circuit configured to bias the gate of each of the plurality of FETs; and

a compensation circuit including a non-linear capacitor connected at a first end to both the source of the first FET and the drain of the second FET, and further connected at a second end to a ground reference, the compensation circuit configured to generate one or more harmonics to substantially cancel a non-linearity effect generated by at least one of the plurality of FETs.

2. The switch of claim 1 wherein the diode comprises a PMOS diode.

3. The switch of claim 1 wherein the capacitance and the diode are coupled in parallel.

4. The RF switch of claim 1 wherein the FET comprises a silicon-on-insulator (SOI) FET.

5. The RF switch of claim 1 wherein the first node is configured to receive an RF signal having a power value and the second node is configured to output the RF signal when the FET is in an ON state.

6. The RF switch of claim 5 wherein the plurality of FETs comprises N FETs connected in series, the quantity N selected to allow the switch circuit to handle the power of the RF signal.

7. The switch of claim 1 wherein the non-linear capacitor includes a metal-oxide-semiconductor (MOS) capacitor.

8. The switch of claim 7 wherein the MOS capacitor includes an FET structure.

9. The switch of claim 8 wherein the one or more harmonics generated by the MOS capacitor is controlled at least in part by a body bias signal provided to the FET structure of the MOS capacitor.

10. The switch of claim 8 wherein the first end of the non-linear capacitor is connected to a drain and a source of the FET structure.

11. A method for operating a radio-frequency (RF) switch, the method comprising:

controlling a plurality of field-effect transistors (FETs) disposed between first and second nodes so that each of the plurality of FETs is in an ON state or an OFF state;

selectively removing surface charge from a respective body of each of the plurality of FETs at low frequencies below a selected value, the selective removal facilitated by a coupling circuit that behaves as an approximately closed circuit at the low frequencies, the coupling circuit including a first circuit coupled in series to a resistance, the first circuit including a capacitance and a diode;

biasing the gate of each of the plurality of FETs when the plurality of FETs is in an OFF state; and

compensating a non-linear effect of the plurality of FETs by applying another non-linear signal to a source or a drain of the plurality of FETs and by generating one or more harmonics to substantially cancel the non-linear effect of the plurality of FETs, the compensating facilitated by a compensation circuit, and the compensation circuit include a non-linear capacitor.

12. The method of claim 11 wherein the coupling circuit further behaves as an approximately open circuit at an operating frequency.

13. The method of claim 12 wherein the capacitance and the diode are coupled in parallel.

14. A radio-frequency (RF) switch module comprising:

a packaging substrate configured to receive a plurality of components;

a semiconductor die mounted on the packaging substrate, the die including a plurality of field-effect transistors (FETs);

a coupling circuit that connects a respective body of each of the plurality of FETs to a respective gate of each of the plurality of FETs, the coupling circuit including a first circuit coupled in series to a resistance, the first circuit including a capacitance and a diode, the coupling circuit configured to behave as an approximately closed circuit at low frequencies below a selected value and as an approximately open circuit at an operating frequency, the approximately closed circuit allowing removal of surface charge from the respective body;

a bias circuit that connects a gate of each of the plurality of FETs to the reference node, the bias circuit configured to bias the gate; and

a compensation circuit including a non-linear capacitor connected at a first end to both the source of the first FET and the drain of the second FET, and further connected at a second end to a ground reference, the compensation circuit configured to generate one or more harmonics to substantially cancel a non-linearity effect generated by at least one of the plurality of FETs.

15. The switch module of claim 14 wherein the semiconductor die comprises a silicon-on-insulator (SOI) die.

16. The switch module of claim 14 wherein the coupling circuit is part of the same semiconductor die as the plurality of FETs.

17. The switch module of claim 14 wherein the coupling circuit is part of a second die mounted on the packaging substrate.

18. The switch module of claim 14 wherein the coupling circuit is disposed at a location outside of the semiconductor die.