Cross point switch

• US 9,595,968 B2
• Filed: 10/13/2015
• Issued: 03/14/2017
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert P., Pitkethly, Scott
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US14/882,262
• Publication Number:
  US 20160036446A1
• Time in Patent Office: 518 Days
• Field of Search: 326/58, 326/57, 326/56
• US Class Current: 1/1
• CPC Class Codes: H03K 17/002 Switching arrangements with several input- or output terminals code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state

Abstract

A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Claims

1. A circuit, comprising:

an input node operable to receive an input signal;

an output node;

an enable circuit operable to receive an enable signal;

a first drive circuit coupled to the input node, the enable circuit, and the output node; and

a second drive circuit coupled to the input node, the enable circuit, and the output node, wherein if the enable signal is in a first state, one of the first drive circuit or the second drive circuit is operable for a period of time to drive at the output node a signal that represents the input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the output node is operable in an impedance state.

2. The circuit of claim 1, further comprising:

a keeper circuit coupled to the enable circuit and further coupled between the input node and the output node.

3. The circuit of claim 1, wherein the first drive circuit comprises:

a NAND gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NAND gate;

a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

4. The circuit of claim 3, wherein the first drive circuit further comprises:

a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and

a falling edge reset circuit coupled to the enable circuit and the second drive circuit.

5. The circuit of claim 1, wherein the second drive circuit comprises:

a NOR gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NOR gate;

a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

6. The circuit of claim 5, wherein the second drive circuit further comprises:

a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and

a rising edge reset circuit coupled to the enable circuit and the first drive circuit.

7. A circuit, comprising:

an input node operable to receive an input signal;

an output node;

an enable circuit operable to receive an enable signal;

a first means for driving coupled to the input node, the enable circuit, and the output node; and

a second means for driving coupled to the input node, the enable circuit, and the output node, wherein if the enable signal is in a first state, one of the first means for driving or the second means for driving is operable for a period of time to drive at the output node a signal that represents the input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the output node is operable in an impedance state.

8. The circuit of claim 7, further comprising:

a keeper circuit coupled to the enable circuit and further coupled between the input node and the output node.

9. The circuit of claim 7, wherein the first means for driving comprises:

a NAND gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NAND gate;

a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

10. The circuit of claim 9, wherein the first means for driving further comprises:

a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and

a falling edge reset circuit coupled to the enable circuit and the second means for driving.

11. The circuit of claim 7, wherein the second means for driving comprises:

a NOR gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NOR gate;

a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

12. The circuit of claim 11, wherein the second means for driving further comprises:

a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and

a rising edge reset circuit coupled to the enable circuit and the first means for driving.

13. A circuit, comprising:

an enable circuit operable to receive an enable signal;

an up drive circuit coupled to the enable circuit; and

a down drive circuit coupled to the enable circuit, wherein if the enable signal is in a first state, one of the up drive circuit or the down drive circuit is operable for a period of time to drive a signal that represents an input signal, wherein the period of time terminates independently of the input signal, and wherein if the enable signal is in a second state, the circuit is operable in an impedance state.

14. The circuit of claim 13, further comprising:

a keeper circuit coupled to the enable circuit.

15. The circuit of claim 13, wherein the up drive circuit comprises:

a NAND gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NAND gate;

a rising edge delay circuit coupled to the first output node of the NAND gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the rising edge delay circuit.

16. The circuit of claim 15, wherein the up drive circuit further comprises:

a latch circuit coupled to the enable circuit, the NAND gate, and the rising edge delay circuit; and

a falling edge reset circuit coupled to the enable circuit and the down drive circuit.

17. The circuit of claim 13, wherein the down drive circuit comprises:

a NOR gate coupled to the enable circuit and including a first output node;

an output drive transistor coupled to the first output node of the NOR gate;

a falling edge delay circuit coupled to the first output node of the NOR gate and the enable circuit; and

a delay circuit coupled in parallel with a portion of the falling edge delay circuit.

18. The circuit of claim 17, wherein the down drive circuit further comprises:

a latch circuit coupled to the enable circuit, the NOR gate, and the falling edge delay circuit; and

a rising edge reset circuit coupled to the enable circuit and the up drive circuit.

19. The circuit of claim 13, further comprising:

an input node operable to receive the input signal.

20. The circuit of claim 13, further comprising:

an output node operable to receive the signal.