Semiconductor device, display device, and method for producing semiconductor device

• US 9,599,871 B2
• Filed: 11/15/2012
• Issued: 03/21/2017
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakata, Yukinobu, Fujita, Tetsuo, Hara, Yoshihito
• Primary Examiner(s): Arendt, Paisley L
• Application Number:
  US14/358,778
• Publication Number:
  US 20150168758A1
• Time in Patent Office: 1,587 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole. The second transparent conductive layer contacts with the drain electrode in the first contact hole to form a contact portion (105), which at least partially overlaps with a gate line layer when viewed along a normal to a substrate.

Claims

1. A semiconductor device comprising:

a substrate and a thin-film transistor,

a gate line layer, and

a source line layer which are supported by the substrate, wherein

the thin-film transistor includes a gate electrode, a gate insulating layer over the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode, and a drain electrode,

the gate line layer includes a gate line and the gate electrode,

the source line layer includes a source line and the source and the drain electrodes,

the semiconductor device further includes;

an interlevel insulating layer which is over the source and the drain electrodes and which includes a first insulating layer that contacts at least with a surface of the drain electrode;

a first transparent conductive layer which is on the interlevel insulating layer and includes a first hole;

a dielectric layer which is on the first transparent conductive layer and which covers a side surface of the first hole of the first transparent conductive layer; and

a second transparent conductive layer over the dielectric layer so as to overlap with at least a portion of the first transparent conductive layer with the dielectric layer interposed between them,

the interlevel insulating layer further includes a second insulating layer between the first insulating layer and the first transparent conductive layer,

the first insulating layer is an inorganic insulating layer and the second insulating layer is an organic insulating layer,

the dielectric layer includes a second hole, the first insulating layer includes a third hole, and the second insulating layer includes a fourth hole,

the interlevel insulating layer and the dielectric layer include a first contact hole, a sidewall of which includes respective side surfaces of the second, the third, and the fourth holes, the sidewall of the first contact hole includes a first portion in which the side surfaces of the second and the third holes are aligned with each other and a second portion in which the side surfaces of the third and the fourth holes are aligned with each other,

the second transparent conductive layer contacts with the drain electrode inside the first contact hole to define a contact portion where the second transparent conductive layer and the drain electrode contact with each other, and

when viewed along a normal to the substrate, at least a portion of the contact portion overlaps with the gate line layer.

2. A display device comprising:

the semiconductor device of claim 1;

a counter substrate which is arranged so as to face the semiconductor device; and

a liquid crystal layer which is arranged between the counter substrate and the semiconductor device, wherein

the display device includes a plurality of pixels which are arranged in a matrix pattern, and

the second transparent conductive layer is divided into multiple portions which are associated with respective pixels so that each of the portions functions as a pixel electrode.

3. The display device of claim 2, wherein the first transparent conductive layer covers 80% or more of each of the pixels.

4. The display device of claim 2, wherein

the second transparent conductive layer includes a plurality of holes cut as slits in each of the pixels, and

the first transparent conductive layer is present at least under those holes and functions as a common electrode.

5. The semiconductor device of claim 1, further comprising a first connecting portion on the substrate, wherein

the gate line layer includes a first lower conductive layer,

the source line layer includes a first upper conductive layer formed in contact with the first lower conductive layer,

the first connecting portion includes:

the first lower conductive layer;

the first upper conductive layer;

the interlevel insulating layer and the dielectric layer extended onto the first upper conductive layer;

an upper transparent connecting layer on the dielectric layer out of a same conductive film as the second transparent conductive layer; and

a lower transparent connecting layer between the interlevel insulating layer and the dielectric layer out of a same conductive film as the first transparent conductive layer,

the interlevel insulating layer and the dielectric layer include second contact hole, in which the upper transparent connecting layer contacts with a portion of the first upper conductive layer, and

the dielectric layer includes a third contact hole, in which the upper transparent connecting layer contacts with a portion of the lower transparent connecting layer.

6. The semiconductor device of claim 5, wherein

the dielectric layer includes a fifth hole,

the first insulating layer includes a sixth hole,

a sidewall of the second contact hole includes respective side surfaces of the fifth and the sixth holes, and

at least a portion of the side surface of the sixth hole is aligned with the side surface of the fifth hole.

7. The semiconductor device of claim 1, wherein the semiconductor layer is an oxide semiconductor layer.

8. The semiconductor device of claim 7, wherein the oxide semiconductor layer is an In—

Ga—

Zn—

O(IGZO) layer.

9. The semiconductor device of claim 1, further comprising a terminal portion on the substrate, wherein

the gate line layer includes a second lower conductive layer,

the source line layer includes a second upper conductive layer which is in contact with the second lower conductive layer,

the terminal portion includes:

the second lower conductive layer;

the second upper conductive layer;

the first insulating layer and the dielectric layer which are extended onto the second upper conductive layer; and

an external connecting layer on the dielectric layer out of a same conductive film as the second transparent conductive layer, and

the first insulating layer and the dielectric layer have a fourth contact hole, respective side surfaces of the first insulating layer and dielectric layer are aligned with each other on a sidewall of the fourth contact hole, and

the external connecting layer contacts with a portion of the second upper conductive layer in the fourth contact hole.

10. The semiconductor device of claim 1, wherein when viewed along a normal to the substrate, the contact portion overlaps in its entirety with the gate line layer.

11. The semiconductor device of claim 1, wherein when viewed along a normal to the substrate, at least a portion of the contact portion overlaps with the gate line or the gate electrode.

12. The semiconductor device of claim 1, wherein when viewed along a normal to the substrate, an outer edge of the second hole of the dielectric layer and an outer edge of the fourth hole of the second insulating layer intersect with each other at two points.

13. The semiconductor device of claim 1, further comprising a protective layer between the semiconductor layer and the source and drain electrodes so as to contact with at least a portion of the semiconductor layer to be a channel region.