Fully digital chaotic differential equation-based systems and methods

• US 9,600,238 B2
• Filed: 02/29/2012
• Issued: 03/21/2017
• Est. Priority Date: 03/01/2011
• Status: Active Grant

• Current Assignee: King Abdullah University of Science and Technology
• Original Assignee: King Abdullah University of Science and Technology
• Inventors: Radwan, Ahmed Gomaa Ahmed, Zidan, Mohammed Affan, Salama, Khaled Nabil
• Primary Examiner(s): SANDIFER, MATTHEW D
• Application Number:
  US13/408,388
• Publication Number:
  US 20120226724A1
• Time in Patent Office: 1,847 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G06F 7/586 using an integer algorithm, e.g. using linear congruential method
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/001 using chaotic signals
• CPC Class Codes: H04L 9/0656 Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher

Abstract

Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Claims

1. A digital circuit, comprising:

three digital state registers; and

three digital logic modules coupled to the three digital state registers, each of the three digital logic modules configured to;

obtain a plurality of first values from two or more digital state registers of the three digital state registers, where a first digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, where a second digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, and where a third digital logic module of the three digital logic modules obtains three first values of the plurality of first values from the three digital state registers;

determine a corresponding second value based upon the two or three first values obtained by that digital logic module and a chaotic differential equation; and

provide the corresponding second value as a respective input to set a state of a corresponding one of the three digital state registers;

where the three digital logic modules are configured to determine the corresponding second values according to a Runge-Kutta Fourth-order numerical solution, a mid-point numerical solution, or an Euler numerical solution to the chaotic differential equation.

2. The digital circuit of claim 1, further configured to generate a chaos shift key (CSK).

3. An apparatus comprising a first digital circuit of claim 1 configured to provide a first set of corresponding second values with a length of 16-bits and a second digital circuit of claim 1 configured to provide a second set of corresponding second values with a length of 32-bits.

4. The apparatus of claim 3, wherein a value of the first set of corresponding second values of the first digital circuit and a corresponding value of the second set of corresponding second values of the second digital circuit are combined to generate a single random output.

5. The digital circuit of claim 1, further comprising a post-processing module configured to combine the state of the three digital state registers to generate a single random output.

6. A digital circuit, comprising:

three digital state registers; and

three digital logic modules coupled to the three digital state registers, each of the three digital logic modules configured to;

obtain a plurality of first values from two or more digital state registers of the three digital state registers, where a first digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, where a second digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, and where a third digital logic module of the three digital logic modules obtains three first values of the plurality of first values from the three digital state registers;

determine a corresponding second value based upon the two or three first values obtained by that digital logic module and a chaotic differential equation, where the chaotic differential equation is a nonlinear jerk equation; and

provide the corresponding second value as a respective input to set a state of a corresponding one of the three digital state registers, where the corresponding second value determined by one of the three digital logic modules comprises a linear component provided to set the state of one of the two or more digital state registers and a nonlinear component provided to set a state of a fourth digital state register.

7. The digital circuit of claim 6, further comprising a post-processing module configured to discard a highest significant bit of at least one of the corresponding second values to generate a single random output.

8. The digital circuit of claim 7, wherein the post-processing module is further configured to discard a lowest significant bit of the at least one of the corresponding second values to generate the single random output.

9. The digital circuit of claim 6, wherein the three digital logic modules do not include multipliers.

10. A digital circuit, comprising:

three digital state registers; and

three digital logic modules coupled to the three digital state registers, each of the three digital logic modules configured to;

obtain a plurality of first values from two or more digital state registers of the three digital state registers, where a first digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, where a second digital logic module of the three digital logic modules obtains two first values of the plurality of first values from two of the three digital state registers, and where a third digital logic module of the three digital logic modules obtains three first values of the plurality of first values from the three digital state registers;

determine a corresponding second value based upon the two or three first values obtained by that digital logic module and a chaotic differential equation, where the three digital logic modules are configured to determine the corresponding second values using shift operations without multiplication operations, where all coefficients of the chaotic differential equation are a power of two; and

provide the corresponding second value as a respective input to set a state of a corresponding one of the three digital state registers.

11. The digital circuit of claim 10, wherein the three digital logic modules are configured to determine the corresponding second values according to a Runge-Kutta Fourth-order numerical solution to the chaotic differential equation.

12. The digital circuit of claim 10, wherein the three digital logic modules are configured to determine the corresponding second values according to a mid-point numerical solution to the chaotic differential equation.

13. The digital circuit of claim 10, wherein the three digital logic modules are configured to determine the corresponding second values according to an Euler numerical solution to the chaotic differential equation.

14. The digital circuit of claim 10, further comprising a post-processing module configured to combine the state of the three digital state registers to generate a single random output.

15. The digital circuit of claim 10, wherein the chaotic differential equation corresponds to a multi-scroll butterfly attractor.

16. The digital circuit of claim 10, wherein the chaotic differential equation corresponds to a multidimensional multi-scroll attractor.

17. A digital circuit, comprising:

a plurality of digital shift registers, each of the plurality of digital shift registers configured to obtain an input and provide an output;

a plurality of digital logic modules coupled to the plurality of digital shift registers, where the plurality of digital logic modules do not include multipliers, each of the plurality of digital logic modules configured to;

obtain outputs from a subset of two or more of the plurality of digital shift registers, where a first digital logic module of the plurality of digital logic modules obtains a first output from two of the plurality of digital shift registers, where a second digital logic module of the plurality of digital logic modules obtains a second output from two of the plurality of digital shift registers, and where a third digital logic module of the plurality of digital logic modules obtains a third output from three of the plurality of digital shift registers; and

provide the input for setting a state of at least one of the subset of two or more of the plurality of digital shift registers, the plurality of digital logic modules each configured to provide the input according to a portion of a numeric solution to a chaotic differential equation, the numeric solution based upon the outputs obtained by that digital logic module; and

a digital clock configured to provide a digital clock signal for operating the plurality of digital shift registers.

18. The digital circuit of claim 17, wherein the plurality of digital shift registers are each configured to provide the output to one or more of the plurality of digital logic modules on a first clock edge of the digital clock signal.

19. The digital circuit of claim 18, wherein the plurality of digital shift registers are each configured to obtain the input from one of the plurality of digital logic modules on a second clock edge of the digital clock signal.

20. The digital circuit of claim 17, further comprising a digital post-processing module configured to generate a chaotic output in response to the inputs received by each of the plurality of digital shift registers.

21. The digital circuit of claim 20, wherein the digital post-processing module is configured to discard a highest significant bit of at least one of the outputs from the subset of two or more of the plurality of digital shift registers to generate the chaotic output.

22. The digital circuit of claim 21, wherein the digital post-processing module is further configured to discard a lowest significant bit of at least one of the outputs from the subset of two or more of the plurality of digital shift registers based upon a distribution of bits in the outputs.

23. The digital circuit of claim 20, wherein the digital post-processing module is configured to combine the states of the plurality of digital shift registers to generate a single random output.

24. The digital circuit of claim 20, wherein the chaotic output is in a fixed-point number format.

25. The digital circuit of claim 17, further configured to generate an output that comprises a chaotic shift key (CSK).

26. A method, comprising:

receiving a clock signal having a first clock state and a second clock state;

obtaining, by each of a plurality of at least three digital logic modules, first values from a subset of a plurality of digital state registers when the clock signal enters the first clock state, where a first one of the plurality of at least three digital logic modules obtains two first values from two of the plurality of digital state registers, where a second one of the plurality of at least three digital logic modules obtains two first values from two of the plurality of digital state registers, and where at least a third one of the plurality of at least three digital logic modules obtains at least three first values from at least three of the plurality of digital state registers;

transforming the first values in each of the plurality of at least three digital logic modules into a corresponding second value based upon a numerical solution to one or more chaotic differential equations, where the one or more chaotic differential equations corresponds to a multi-scroll butterfly attractor;

writing the corresponding second values into a corresponding one of the plurality of digital state registers when the clock signal enters the second clock state; and

providing a control signal to adjust parameters of the chaotic differential equations to modify the multi-scroll butterfly attractor.

27. The method of claim 26, further comprising providing at least one of the corresponding second values as a random number output.

28. The method of claim 27, further comprising discarding a highest significant bit of the at least one corresponding second value.

29. The method of claim 27, further comprising discarding a lowest significant bit of the at least one corresponding second value.

30. The method of claim 27, further comprising combining a plurality of the corresponding second values to form the random number output.

31. The method of claim 27, wherein the random number output comprises a fixed-point number.