Calculation method and apparatus for evaluating response time of computer system in which plurality of units of execution can be run on each processor core

• US 9,600,290 B2
• Filed: 12/15/2014
• Issued: 03/21/2017
• Est. Priority Date: 12/17/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Inoue, Hiroshi
• Primary Examiner(s): VU, TUAN A
• Application Number:
  US14/570,203
• Publication Number:
  US 20150169380A1
• Time in Patent Office: 827 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5088 involving task migration

Abstract

A calculation method for evaluating response time in a computer system in which a plurality of units of execution are run on individual processor cores. The calculation method evaluates response time in a computer system in which a plurality of units of execution are run in parallel on individual processor cores while sharing internal hardware resources. The method includes the steps of: normalizing the utilization state of the computer system with the state of parallelism of the units of execution and evaluating the utilization state; and calculating an expected value of response time in a desired state of parallelism of the units of execution from the normalized utilization state on the basis of queueing theory in which changes in average single-thread performance of the units of execution according to the parallel running state are taken into account.

Claims

1. A computer program product for evaluating a response time in a computer system, wherein a plurality of units of execution are run in parallel on individual processor cores while sharing internal hardware resources, the computer program product comprising a computer readable storage medium having computer readable instructions embodied therewith, the instructions executable by a computer to cause the computer to:

normalize a utilization state of the computer system with the state of parallelism of the units of execution and evaluate the utilization state, wherein normalizing the utilization state comprises obtaining a utilization state of all CPU threads of the processor cores, and calculating a normalized utilization value from the obtained utilization state of each CPU thread with reference to a case in which a number of active threads is 1;

calculate an expected value of response time in a desired state of parallelism of the units of execution from the normalized utilization state on the basis of queueing theory, wherein changes in an average single-thread performance of the units of execution according to the parallel running state are taken into account;

determine a degree of parallelism or a combination of degrees of parallelism at which the calculated expected value of response time is optimized as the state of parallelism of the units of execution used in the utilization state; and

update the state of parallelism of the units of execution used on the basis of the calculated result of the expected value of response time in the state of parallelism,

wherein the plurality of units of execution are run in parallel on the individual processor cores using a simultaneous multi-threading (SMT) function, and the expected value of response time is calculated while the SMT function is enabled.

2. The computer program product according to claim 1, wherein accounting for changes in the average single-thread performance refers to calculating a waiting time in a queue by taking changes in the average single-thread performance according to a number of simultaneous operations of units of execution in a processor core at a moment as changes in an average service factor.

3. The computer program product according to claim 1, wherein:

the computer system includes a plurality of processor cores; and

the expected value of response time is calculated by;

calculating a waiting time in a queue in which the number of units of execution in each processor core is the number of windows;

calculating the migratability probability that at least one processor core capable of accepting a task from another processor core is present in a queue with the number of windows across the plurality of processor cores; and

calculating an expected value of an average response time as the response time from the waiting time and the migratability probability.

4. The computer program product according to claim 1, wherein evaluating the utilization state comprises calculating normalized CPU utilization of the computer system from the single-thread performance of the units of execution at the individual degrees of parallelism and the utilization of the individual units of execution.

5. The computer program product according to claim 1,

wherein the computer is separated from the computer system to be evaluated,

evaluating the utilization state comprises assuming a plurality of utilization states of the computer system, and the instructions executable by the computer further cause the computer to:

record the state of parallelism of units of execution used in association with the assumed individual plurality of utilization states.

6. The computer program product according to claim 1:

wherein the unit of execution is a hardware thread.

7. A calculation apparatus for evaluating response time in a computer system, wherein a plurality of units of execution are run in parallel on individual processor cores while sharing internal hardware resources, the apparatus comprising:

a memory storing a computer program; and

a processor configured to execute the computer program, wherein the computer program is configured to;

normalize a utilization state of the computer system with the state of parallelism of the units of execution and evaluate the utilization state, wherein normalizing the utilization state comprises obtaining a utilization state of all CPU threads of the processor cores, and calculating a normalized utilization value from the obtained utilization state of each CPU thread with reference to a case in which a number of active threads is 1;

calculate an expected value of response time in a desired state of parallelism of the units of execution from the normalized utilization state on the basis of queueing theory, wherein changes in an average single-thread performance of the units of execution according to the parallel running state are taken into account;

determine a degree of parallelism or a combination of degrees of parallelism at which the calculated expected value of response time is optimized as the state of parallelism of the units of execution used in the utilization state; and

update the state of parallelism of the units of execution used on the basis of the calculated result of the expected value of response time in the state of parallelism,

wherein the plurality of units of execution are run in parallel on the individual processor cores using a simultaneous multi-threading (SMT) function, and the expected value of response time is calculated while the SMT function is enabled.

8. The calculation apparatus according to claim 7, wherein the computer system includes a plurality of processor cores, and the computer program is further configured to:

calculate a waiting time in a queue, wherein the number of units of execution in each processor core is the number of windows;

calculate the migratability probability that at least one processor core capable of accepting a task from another processor core is present in a queue with the number of windows across the plurality of processor cores; and

calculate an expected value of an average response time as the response time from the waiting time and the migratability probability.

9. The calculation apparatus according to claim 7, wherein the calculation apparatus is the computer system.

10. The calculation apparatus according to claim 7, wherein the calculation apparatus is separated from the computer system to be evaluated, and evaluating the utilization state comprises assuming a plurality of utilization states of the computer system, wherein the computer program is further configured to:

record the state of parallelism of units of execution used in association with the assumed individual plurality of utilization states.