Monitoring accesses to memory in a multiprocessor system
First Claim
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1. A method in a multiprocessor system, the method comprising:
- receiving a plurality of signals during execution of a sequence of code, the plurality of signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code, wherein the multiprocessor system includes a plurality of processing elements, a sequencer, and memory to which each of the processing elements and the sequencer has access, wherein the sequencer is a sequence processor adapted to generate the sequence of code to be executed by the plurality of processing elements, wherein the sequencer is distinct from the plurality of processing elements, and wherein the generated sequence of code includes actions to be performed by the plurality of processing elements under control of the sequence processor;
at the instances, applying the memory access rules for memory accesses by the plurality of processing elements, wherein the plurality of signals update the memory access rules dynamically as execution of the sequence of code progresses; and
in the event of a memory access by a processing element violating one or more of the memory access rules, generating a warning signal.
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Abstract
Embodiments of the present invention provide methods and apparatus in a multiprocessor system, whereby a set of rules relating to memory access are created and implemented in a hardware element. The rules can be updated dynamically, for example by the sequence processor (or sequencer) used to control the multiple processing elements.
60 Citations
15 Claims
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1. A method in a multiprocessor system, the method comprising:
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receiving a plurality of signals during execution of a sequence of code, the plurality of signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code, wherein the multiprocessor system includes a plurality of processing elements, a sequencer, and memory to which each of the processing elements and the sequencer has access, wherein the sequencer is a sequence processor adapted to generate the sequence of code to be executed by the plurality of processing elements, wherein the sequencer is distinct from the plurality of processing elements, and wherein the generated sequence of code includes actions to be performed by the plurality of processing elements under control of the sequence processor; at the instances, applying the memory access rules for memory accesses by the plurality of processing elements, wherein the plurality of signals update the memory access rules dynamically as execution of the sequence of code progresses; and in the event of a memory access by a processing element violating one or more of the memory access rules, generating a warning signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A hardware element for use in a multiprocessor system, the hardware element being adapted to perform a method in the multiprocessor system, wherein the method comprises:
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receiving a plurality of signals during execution of a sequence of code, the plurality of signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code, wherein the multiprocessor system includes a plurality of processing elements, a sequencer, and memory to which each of the processing elements and the sequencer has access, wherein the sequencer is a sequence processor adapted to generate the sequence of code to be executed by the plurality of processing elements, wherein the sequencer is distinct from the plurality of processing elements, and wherein the generated sequence of code includes actions to be performed by the plurality of processing elements under control of the sequence processor; at the instances, applying the memory access rules for memory accesses by the plurality of processing elements, wherein the plurality of signals update the memory access rules dynamically as execution of the sequence of code progresses; and in the event of a memory access by a processing element violating one or more of the memory access rules, generating a warning signal. - View Dependent Claims (13)
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14. A multiprocessor system, comprising:
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a plurality of processing elements; a sequencer adapted to generate a sequence of code to be executed by the plurality of processing elements, wherein the sequencer is a sequence processor, wherein the sequencer is distinct from the plurality of processing elements, and wherein the generated sequence of code includes actions to be performed by the plurality of processing elements under control of the sequence processor; memory to which each of the processing elements and the sequencer has access; and a hardware element, wherein the hardware element is adapted to perform a method in the multiprocessor system and wherein the method comprises; receiving a plurality of signals during execution of the sequence of code, the signals indicating a plurality of memory access rules to be applied at instances during further execution of the sequence of code; at the instances, applying the memory access rules for memory accesses by the plurality of processing elements, wherein the plurality of signals update the memory access rules dynamically as execution of the sequence of code progresses; and in the event of a memory access by a processing element violating one or more of the memory access rules, generating a warning signal. - View Dependent Claims (15)
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Specification