System, apparatus and method for integrating non-peripheral component interconnect (PCI) resources into a personal computer system

• US 9,600,433 B2
• Filed: 04/25/2014
• Issued: 03/21/2017
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Mandhani, Arvind, Han, Woojong, Shoemaker, Ken, Athreya, Madhu, Wagh, Mahesh, Thakkar, Shreekant S.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US14/261,934
• Publication Number:
  US 20140237154A1
• Time in Patent Office: 1,061 Days
• Field of Search: 710305-313, 710104-110
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Claims

1. A processor comprising:

an adapter adapted on a single semiconductor die to communicate with a first component via a first interconnect compatible with a first protocol and to communicate with an interface via a second interconnect compatible with a second protocol;

the interface adapted on the single semiconductor die and coupled to the adapter, the interface to perform enumeration for a plurality of heterogeneous resources coupled to a third interconnect; and

the third interconnect adapted on the single semiconductor die to provide interconnection and routing of communications between the interface and the plurality of heterogeneous resources, each including an intellectual property (IP) core and a shim, wherein the shim is to couple between the IP core and the third interconnect, the processor to operate in accordance with the first protocol and the IP core to operate in accordance with the second protocol.

2. The processor of claim 1, wherein the interface is to translate configuration cycles of the first protocol into a format for the second protocol, wherein the first protocol is a peripheral component interconnect (PCI)-compliant protocol.

3. The processor of claim 1, wherein the interface is to perform operations that are common across the plurality of heterogeneous resources, and each shim is to perform operations that are specific to the corresponding IP core, wherein the shim is to communicate with the corresponding IP core in accordance with the second protocol.

4. The processor of claim 1, wherein the third interconnect comprises an auto-generated interconnect fabric.

5. The processor of claim 1, wherein the interface is to route accesses to a header to a corresponding shim, and the shim is to implement the header for the corresponding IP core, wherein the interface is to further route accesses to a device memory space to the corresponding shim.

6. The processor of claim 1, wherein at least one of the plurality of heterogeneous resources is of a third party.

7. The processor of claim 1, wherein the processor comprises a system on a chip (SoC) and wherein the SoC is to couple to a second processor, the second processor to execute a personal computer-based operating system.

8. The processor of claim 2, wherein the PCI-compliant protocol comprises a PCI Express protocol.

9. The processor of claim 3, wherein the common operations include address translation and ordering of transactions received from the first component, and the specific operations include power management and error handling.

10. The processor of claim 5, wherein the corresponding shim is to consume read-write operations to the header and to communicate other transactions to the corresponding IP core.

11. The processor of claim 2, wherein the interface is to perform address translation to translate a re-locatable PCI address into a fixed advanced extensible interface (AXI)/open core protocol (OCP) address and to translate the fixed AXI/OCP address into the relocatable PCI address.

12. The processor of claim 9, wherein the ordering is to satisfy a producer-consumer model of the first protocol.

13. A system-on-chip (SoC) comprising:

a processor adapted on a semiconductor die;

a host interface adapted on the semiconductor die to couple to the processor, the host interface to couple the processor to a memory and an adapter;

the adapter to couple to the host interface to communicate with the host interface via a first interconnect to operate according to a peripheral component interconnect express (PCIe)-compatible protocol and to communicate with a second interface via a second interconnect to operate according to an advanced extensible interface (AXI)/open core protocol (OCP)-compatible protocol;

the second interface adapted on the semiconductor die to couple to the adapter, the second interface to perform common functionality for a plurality of heterogeneous resources to couple to a third interconnect; and

the third interconnect adapted on the semiconductor die to couple the second interface to the plurality of heterogeneous resources, each of the plurality of heterogeneous resources including a core and an interface logic, wherein the SoC is to operate according to the PCIe-compatible protocol and at least one of the cores is to operate according to the AXI/OCP protocol.

14. The SoC of claim 13, further comprising a system comprising an ultra mobile system, wherein the processor is to execute using the PCIe-compatible protocol.

15. The SoC of claim 13, wherein the second interface includes an address redirection table.

16. The SoC of claim 14, wherein the second interface is to translate configuration cycles from the processor into a format for the AXI/OCP protocol, the second interface to perform address translation to translate a re-locatable PCIe address into an OCP address.

17. The SoC of claim 16, wherein each interface logic is to perform operations that are specific to the corresponding core, the common functionality including address translation and ordering of transactions received from the processor, and the specific operations including power management and error handling.

18. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

communicating, via an adapter of a system on a chip (SoC), with a first component according to a peripheral component interconnect (PCI)-compatible protocol and communicating with a first interface according to a second protocol;

performing address translation and ordering of transactions received from the first component in the first interface;

translating configuration cycles of the PCI-compatible protocol into a format for the second protocol; and

communicating between the first interface and a plurality of heterogeneous resources, via an interconnect, each of the plurality of heterogeneous resources including a core and an interface logic, wherein the SoC is to operate according to the PCI-compatible protocol and at least some of the cores to operate according to the second protocol.

19. The machine-readable medium of claim 18, wherein the method further comprises performing the address translation to translate a re-locatable address into a fixed address.

20. The machine-readable medium of claim 18, wherein the method further comprises performing operations that are common across the plurality of heterogeneous resources in the first interface, and performing operations that are specific to the corresponding core in the corresponding interface logic.