Shift register
First Claim
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1. A shift register comprising:
- a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, each of the plurality of stages including an output buffer unit for forwarding the scan pulse and an output control unit for controlling an output from the output buffer unit,wherein the output control unit provided to an nth stage includes;
a first switching device configured to connect a high potential voltage line to a first node when the first switching device is turned on in response to a start pulse or a scan pulse from a (n−
1)th stage,a second switching device configured to connect the first node to a low potential voltage line when the second switching device is turned on in response to a scan pulse from a (n+1)th stage,a third switching device configured to connect the first node to the low potential voltage line when the third switching device is turned on in response to a signal state of a second node, and, anda fourth switching device configured to connect a first AC power line to the second node when the fourth switching device is turned on according to a first AC voltage from the first AC power line,wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof,wherein a clock pulse is applied to the first electrode,wherein the at least one of the plurality of switching device includes;
a plurality of sub-first electrodes formed parallel to one another, and having first ends and second ends,a connecting first electrode connecting the plurality of sub-first electrodes at the first ends of the plurality of sub-first electrodes,a plurality of sub-second electrodes formed parallel to one another, and having first ends and second ends, anda connecting second electrode connecting the plurality of sub-second electrodes at the first ends of the plurality of sub-second electrodes, andwherein;
the connecting second electrode, the plurality of sub-first electrodes and sub-second electrodes, and the second ends of the plurality of sub-first electrodes overlap with the gate electrode, andthe second ends of the plurality of sub-second electrodes and the connecting first electrode do not overlap the gate electrode.
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Abstract
The present invention relates to a shift register in which a structure of a switching device of an output buffer unit is changed for reducing power consumption. The shift register includes a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein the at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof with a size different from a second area at which the gate electrode overlaps with a second electrode thereof.
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Citations
7 Claims
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1. A shift register comprising:
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a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, each of the plurality of stages including an output buffer unit for forwarding the scan pulse and an output control unit for controlling an output from the output buffer unit, wherein the output control unit provided to an nth stage includes; a first switching device configured to connect a high potential voltage line to a first node when the first switching device is turned on in response to a start pulse or a scan pulse from a (n−
1)th stage,a second switching device configured to connect the first node to a low potential voltage line when the second switching device is turned on in response to a scan pulse from a (n+1)th stage, a third switching device configured to connect the first node to the low potential voltage line when the third switching device is turned on in response to a signal state of a second node, and, and a fourth switching device configured to connect a first AC power line to the second node when the fourth switching device is turned on according to a first AC voltage from the first AC power line, wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof, wherein a clock pulse is applied to the first electrode, wherein the at least one of the plurality of switching device includes; a plurality of sub-first electrodes formed parallel to one another, and having first ends and second ends, a connecting first electrode connecting the plurality of sub-first electrodes at the first ends of the plurality of sub-first electrodes, a plurality of sub-second electrodes formed parallel to one another, and having first ends and second ends, and a connecting second electrode connecting the plurality of sub-second electrodes at the first ends of the plurality of sub-second electrodes, and wherein; the connecting second electrode, the plurality of sub-first electrodes and sub-second electrodes, and the second ends of the plurality of sub-first electrodes overlap with the gate electrode, and the second ends of the plurality of sub-second electrodes and the connecting first electrode do not overlap the gate electrode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A shift register comprising:
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a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof, wherein a clock pulse is applied to the first electrode, wherein the at least one of the plurality of switching device includes; a plurality of sub-first electrodes formed parallel to one another, a connecting first electrode connecting the plurality of sub-first electrodes, a plurality of sub-second electrodes formed parallel to one another, and a connecting second electrode connecting the plurality of sub-second electrodes, and wherein the plurality of sub-first electrodes are formed to overlap with the gate electrode, the connecting first electrode is formed not to overlap with the gate electrode, the plurality of sub-second electrodes and the connecting second electrode are formed to overlap with the gate electrode, wherein each of the plurality of stages includes an output buffer unit for forwarding the scan pulse and an output control unit for controlling an output from the output buffer unit, and the output buffer unit includes the at least one of the plurality of switching devices having the first area being smaller than the second area, wherein the output buffer unit includes; a pull-up switching device to be turned on/off depending on a signal state of a first node, and to connect one of clock transmission lines to an output terminal of one of the plurality of stages when the pull-up switching device is turned on, a first pull-down switching device to be turned on/off depending on a signal state of a second node, and to connect the output terminal to a low potential voltage line when the first pull-down switching device is turned on, and a second pull-down switching device to be turned on/off depending on a signal state of a third node, and to connect the output terminal to the low potential voltage line when the second pull-down switching device is turned on, wherein the low potential voltage line transmits a low potential voltage and the clock transmission lines transmit a plurality of clock pulses having phases different from one another, and the at least one of the plurality of switching devices having the first area being smaller than the second area is the pull-up switching device, wherein the output control unit provided to an nth stage includes; a first switching device to be turned on/off in response to a start pulse or a scan pulse from a (n−
1)th stage, and to connect a high potential voltage line to the first node when the first switching device is turned on,a second switching device to be turned on/off in response to the scan pulse from a (n+1)th stage, and to connect the first node to the low potential voltage line when the second switching device is turned on, a third switching device to be turned on/off depending on the signal state of the second node, and to connect the first node to the low potential voltage line when the third switching device is turned on, a fourth switching device to be turned on/off according to a first AC voltage from a first AC power line, and to connect the first AC power line to the second node when the fourth switching device is turned on, a fifth switching device to be turned on/off depending on the signal state of the first node, and to connect the second node to the low potential voltage line when the fifth switching device is turned on, a sixth switching device to be turned on/off in response to the start pulse or the scan pulse from the (n−
1)th stage, and to connect the second node to the low potential voltage line when the sixth switching device is turned on,a seventh switching device to be turned on/off depending on the signal state of the third node, and to connect the first node to the low potential voltage line when the seventh switching device is turned on, an eighth switching device to be turned on/off according to a second AC voltage from a second AC power line, and to connect the second AC power line to the third node when the eighth switching device is turned on, a ninth switching device to be turned on/off depending on the signal state of the first node, and to connect the third node to the low potential voltage line when the ninth switching device is turned on, and a tenth switching device to be turned on/off in response to the start pulse or the scan pulse from the (n−
1)th stage, and to connect the third node to the low potential voltage line when the tenth switching device is turned on,wherein the second AC voltage has a mode of a phase inverted by 180 degrees with respect to the first AC voltage, a high potential voltage from the high potential voltage line is higher than the low potential voltage from the low potential voltage line, and at least one of the first to tenth switching devices has the first area being smaller than the second area.
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Specification