Sense amplifier

• US 9,601,165 B1
• Filed: 09/24/2015
• Issued: 03/21/2017
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Dray, Cyrille, Boujamaa, El Mehdi
• Primary Examiner(s): Alrobaie, Khamdan
• Application Number:
  US14/864,702
• Publication Number:
  US 20170092337A1
• Time in Patent Office: 544 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.

Claims

1. A sense amplifier circuit comprising:

a first path including a first transistor, a second transistor, and an intermediate node coupled between the first and second transistors;

switch circuitry to selectively couple a reference cell to the first path during a first phase of a read operation and to selectively couple a memory cell to the first path during a second phase of the read operation to generate a voltage at the intermediate node that is indicative of a value of a bit stored by the memory cell; and

a bias circuit coupled to the first and second transistors, the bias circuit to generate a first current based on a current through the first transistor and pass the first current through a third transistor to provide a bias voltage to a gate terminal of the second transistor.

2. The circuit of claim 1, wherein the third transistor is a diode-connected transistor.

3. The circuit of claim 2, wherein the bias circuit includes a fourth transistor with a gate terminal coupled to a gate terminal of the first transistor to copy the current of the first transistor.

4. The circuit of claim 1, wherein the intermediate node is a first intermediate node, wherein the bias circuit is a first bias circuit, wherein the bias voltage is a first bias voltage, and wherein the circuit further comprises:

a second path including a fourth transistor, a fifth transistor, and a second intermediate node coupled between the fourth and fifth transistors; and

a second bias circuit coupled to the fourth and fifth transistors, the second bias circuit to generate a second current based on a current through the fourth transistor and pass the second current through a sixth transistor to provide a second bias voltage to a gate terminal of the fifth transistor;

wherein the switch circuitry is to selectively couple the memory cell to the second path during the first phase and is to selectively couple a second reference cell to the second path during the second phase.

5. The circuit of claim 4, wherein the gate terminals of the second and fifth transistors are coupled to one another such that the first bias voltage is the same as the second bias voltage.

6. The circuit of claim 4, further comprising a latch circuit that is direct current (DC) coupled between the first and second intermediate nodes, wherein the latch circuit is to selectively activate at or near an end of the second phase to generate a digital output signal based on a voltage difference between the first and second intermediate nodes.

7. The circuit of claim 6, wherein the latch circuit includes a first enable transistor coupled between pull-up transistors of the latch circuit and a supply terminal and a second enable transistor coupled between pull-down transistors of the latch circuit and a ground terminal, wherein the first and second enable transistors are to turn on to activate the latch circuit.

8. The circuit of claim 6, further comprising a cutoff transistor coupled between the first and second paths to turn off responsive to activation of the latch circuit.

9. The circuit of claim 8, wherein the cutoff transistor is to provide amplification gain to the first and second intermediate nodes during the second phase.

10. The circuit of claim 1, further comprising a first trimmable resistor coupled between the switch circuitry and the memory cell and a second trimmable resistor coupled between the switch circuitry and the reference cell.

11. The circuit of claim 1, wherein the memory cell is a resistive memory cell.