Storage device including nonvolatile memory and memory controller and operating method of retiming circuit interfacing communication between nonvolatile memory and memory controller

• US 9,601,171 B2
• Filed: 03/23/2015
• Issued: 03/21/2017
• Est. Priority Date: 06/13/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Hyunjin, Lee, Seonkyoo, Ihm, Jeongdon, Jeon, Youngjin
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/665,148
• Publication Number:
  US 20150364173A1
• Time in Patent Office: 729 Days
• Field of Search: 365/191, 365/193, 365/189.03
• US Class Current: 1/1
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller.

Claims

1. A storage device comprising:

a nonvolatile memory; and

a memory controller configured to control the nonvolatile memory and configured to transmit a first timing signal to the nonvolatile memory at a read operation,

wherein the nonvolatile memory comprises;

a nonvolatile memory device configured to output read data and a second timing signal in response to the first timing signal; and

a retiming circuit configured to detect a locking delay based on the first timing signal, configured to produce a third timing signal from the second timing signal using the detected locking delay, configured to retime the read data by latching the read data in synchronization with the third timing signal, and configured to output the third timing signal and the retimed read data to the memory controller.

2. The storage device of claim 1, wherein the retiming circuit comprises:

a first timing reception node configured to receive the first timing signal from the memory controller;

a first timing transmission node configured to transmit to the nonvolatile memory the first timing signal received through the first timing reception node;

a second timing reception node configured to receive the second timing signal from the nonvolatile memory;

a delay locked loop configured to detect the locking delay from the first timing signal received through the first timing reception node and configured to produce the third timing signal from the second timing signal received through the second timing reception node, using the detected locking delay; and

a second timing transmission node configured to output the third timing signal to the memory controller.

3. The storage device of claim 2, wherein the retiming circuit further comprises:

a data reception node configured to receive the read data;

a flip-flop configured to receive and output the read data, received through the data reception node, in synchronization with the third timing signal output from the delay locked loop; and

a data transmission node configured to output an output of the flip-flop to the memory controller as the retimed read data.

4. The storage device of claim 1, wherein the memory controller is further configured to transmit write data and a fourth timing signal to the nonvolatile memory, and

the retiming circuit is further configured to detect a second locking delay from the fourth timing signal and to produce a fifth timing signal from the fourth timing signal using the second locking delay.

5. The storage device of claim 4, wherein the retiming circuit is further configured to retime the write data by latching the write data in synchronization with the fifth timing signal, and configured to output the fifth timing signal and the retimed write data to the nonvolatile memory.

6. The storage device of claim 5, wherein the retiming circuit comprises:

a timing reception node configured to receive the fourth timing signal from the memory controller;

a delay locked loop configured to detect the second locking delay from the fourth timing signal and configured to produce the fifth timing signal from the fourth timing signal using the second locking delay; and

a timing transmission node configured to transmit the fifth timing signal to the nonvolatile memory.

7. The storage device of claim 6, wherein the retiming circuit further includes:

a data reception node configured to receive the write data from the memory controller;

a flip-flop configured to receive and output the write data in synchronization with the fifth timing signal; and

a data transmission node configured to transmit an output of the flip-flop to the nonvolatile memory as the retimed write data.

8. The storage device of claim 5, wherein the retiming circuit comprises:

a decoder configured to receive a control signal from the memory controller, to determine a read operation or write operation of the nonvolatile memory in response to the control signal, and to output an operating signal indicating the read operation or the write operation of the nonvolatile memory;

a timing signal processing unit configured to receive the first, second and fourth timing signals from the memory controller and the nonvolatile memory, and configured to produce the third and fifth timing signals based on the first, second and fourth timing signals; and

a data retiming unit configured to receive the read and write data from the memory controller and the nonvolatile memory, and configured to retime the read data and write data using the third and fifth timing signals.

9. The storage device of claim 8, wherein the timing signal processing unit comprises:

a first timing reception node configured to receive the first timing signal from the memory controller;

a first timing transmission node configured to transmit the first timing signal to the nonvolatile memory;

a second timing reception node configured to receive the second timing signal from the nonvolatile memory;

a third timing reception node configured to receive the fourth timing signal from the memory controller;

a multiplexer configured to output the first timing signal and the second timing signal at a read operation, and configured to output the fourth timing signal at a write operation, in response to the operating signal;

a delay locked loop configured to detect the locking delay from the first timing signal at the read operation, configured to produce the third timing signal from the second timing signal using the detected locking delay, configured to detect the second locking delay from the fourth timing signal at the write operation, and configured to produce the fifth timing signal from the fourth timing signal using the second locking delay;

a second timing transmission node configured to transmit the third timing signal to the memory controller; and

a third timing transmission node configured to transmit the fifth timing signal to the nonvolatile memory.

10. The storage device of claim 8, wherein the data retiming unit comprises:

a first data reception node configured to receive the read data from the nonvolatile memory;

a first flip-flop configured to receive and output the read data in synchronization with the third timing signal;

a first data transmission node configured to transmit an output of the first flip-flop to the memory controller as the retimed read data;

a second data reception node configured to receive the write data from the memory controller;

a second flip-flop configured to receive and output the write data in synchronization with the fifth timing signal; and

a second data transmission node configured to transmit an output of the second flip-flop to the nonvolatile memory as the retimed write data.

11. A storage device comprising:

a nonvolatile memory including one or more nonvolatile memory device;

a random access memory (RAM);

a memory controller configured to control the nonvolatile memory and configured to transmit a first timing signal to the nonvolatile memory at a read operation; and

a retiming circuit configured to detect a locking delay based on the first timing signal,

wherein the one or more nonvolatile memory device is configured to output read data and a second timing signal in response to the first timing signal, and

the retiming circuit is configured produce a third timing signal from the second timing signal using the detected locking delay, configured to retime the read data by latching the read data in synchronization with the third timing signal, and configured to output the third timing signal and the retimed read data to the memory controller.

12. The storage device of claim 11, wherein the retiming circuit includes:

a timing signal processing circuit configured to receive the first and second timing signals, and configured to produce the third timing signal based on the first and second timing signals; and

a data retiming circuit configured to receive the read data, and configured to retime the read data using the third timing signal.

13. The storage device of claim 11, wherein the retiming circuit includes a delay locked loop configured to detect the locking delay from the first timing signal, and configured to produce the third timing signal from the second timing signal, using the detected locking delay.

14. The storage device of claim 11, wherein the memory controller is configured to transmit write data and a fourth timing signal to the nonvolatile memory, and

the retiming circuit is configured to detect a second locking delay from the fourth timing signal and to produce a fifth timing signal from the fourth timing signal using the second locking delay.

15. The storage device of claim 11, wherein the retimed read data is delayed from the read data as much as a quarter period of the third timing signal.

16. The storage device of claim 11, wherein the locking delay is detected while the first timing signal toggles two times.

17. The storage device of claim 11, wherein the nonvolatile memory includes two or more nonvolatile memory devices, and

two or more nonvolatile memory devices are connected to the retiming circuit in common.

18. The storage device of claim 11, wherein the first timing signal is a read enable signal that is toggled by the memory controller at the read operation, and

the second timing signal is a data strobe signal produced by the nonvolatile memory on the basis of the read enable signal.