Semiconductor device and the method of manufacturing the same

• US 9,601,334 B2
• Filed: 04/20/2016
• Issued: 03/21/2017
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Nishimura, Takeyoshi
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US15/133,627
• Publication Number:
  US 20160233090A1
• Time in Patent Office: 335 Days
• Field of Search: 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device according to the invention includes p-type well region 3 and n⁺ source region 4, both formed selectively in the surface portion of n⁻ drift region 2; trench 6 in contact with n⁺ source region 4 and extending through p-type well region 3 into n⁻ drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n⁻ lightly doped region 21 in n⁻ drift region 2, n⁻ lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n⁻ lightly doped region 21 covering the bottom surface of trench 6.

The semiconductor device according to the invention and the method of manufacturing the semiconductor device according to the invention facilitate lowering the ON-state voltage, preventing the breakdown voltage from lowering, lowering the gate capacitance, and reducing the manufacturing costs.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

(a) forming a trench in a first semiconductor region of a first conductivity type;

(b) introducing an impurity of the first conductivity type selectively into a surface portion of the first semiconductor region for setting a concentration of the impurity of the first conductivity type in the surface portion of the first semiconductor region exposed to a side wall of the trench excluding a corner portion of the trench to be high;

(c) forming a first electrode in the trench with a first insulator film interposed between the side wall of the trench and the first electrode, step (c) being conducted after the step (b);

(d) forming a control electrode in the trench with a second insulator film interposed between the side wall of the trench and the control electrode, the control electrode being formed above the first electrode; and

(e) diffusing the impurity of the first conductivity type introduced into the surface portion of the first semiconductor region for forming another semiconductor region of the first conductivity type on the side wall of the trench, the another semiconductor region being not so deep as to reach the corner portion of the trench, the another semiconductor region being doped more heavily than the first semiconductor region.

2. The method according to claim 1, wherein impurity ions of the first conductivity type are implanted at an oblique angle between 45 degrees and 80 degrees to a surface of the first semiconductor region in the step (b).