Magnetic contacts

• US 9,601,468 B2
• Filed: 05/04/2016
• Issued: 03/21/2017
• Est. Priority Date: 08/13/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Skinner, Michael P., Ossiander, Teodora, Albers, Sven, Seidemann, Georg
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US15/146,811
• Publication Number:
  US 20160247785A1
• Time in Patent Office: 321 Days
• US Class Current: 1/1
• CPC Class Codes: H01F 7/04 Means for releasing the attractive force
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/11332 using a powder
• CPC Class Codes: H01L 2224/11522 Auxiliary means therefor, e.g. for self-assembly activation
• CPC Class Codes: H01L 2224/132 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13298 Fillers
• CPC Class Codes: H01L 2224/13355 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13357 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/1336 Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/13444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13464 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/13469 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/811 the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/81139 Guiding structures on the body
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Claims

1. A method, comprising:

embedding a first magnet into a first integrated circuit substrate, or a first electrical routing feature of the first integrated circuit substrate;

generating a magnetic field between the first electrical routing feature of the first integrated circuit substrate and a second electrical routing feature of a second integrated circuit substrate, wherein the magnetic field extends across a gap between the first and second electrical routing features; and

forming an interconnect structure between the first and second electrical routing features, wherein the interconnect structure comprises a plurality of conductive magnetic particles.

2. The method of claim 1, wherein one or more of the first integrated circuit substrate and the second integrated circuit substrate includes a die.

3. The method of claim 2, wherein generating the magnetic field includes embedding a second magnet into the second electrical routing feature or the second integrated circuit substrate.

4. The method of claim 3, wherein generating the magnetic field includes positioning the first and second electrical routing features in substantial proximity such that corresponding first and second magnetic fields of the first and second magnets overlap along said gap.

5. The method of claim 1, wherein forming the interconnect structure between the first and second electrical routing features includes applying the plurality of conductive magnetic particles to one or more of the first and second integrated circuit substrates.

6. The method of claim 1, wherein forming the interconnect structure between the first and second electrical routing features includes dispensing the plurality of conductive magnetic particles into a gap between the first and second integrated circuit substrates.

7. A method comprising:

reducing a magnetic field between a first electrical routing feature of a first integrated circuit substrate and a second electrical routing feature of a second integrated circuit substrate, wherein the magnetic field is generated by a first magnet disposed within the first integrated circuit substrate, or the first electrical routing feature, a plurality of conductive magnetic particles are disposed in a gap between the first and second electrical routing features and reducing the magnetic field reduces a magnetic attraction between the conductive magnetic particles and the first and second electrical routing features; and

separating the first integrated circuit substrate from the second integrated circuit substrate.

8. The method of claim 7, wherein the second integrated circuit substrate includes one or more magnets coupled with the second electrical routing features, and reducing the magnetic field includes heating the one or more magnets to a Curie temperature of the one or more magnets.

9. The method of claim 7, wherein one or more of the first integrated circuit substrate and the second integrated circuit substrate includes a die.