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Semiconductor device for reducing gate wiring length

  • US 9,601,572 B2
  • Filed: 04/08/2015
  • Issued: 03/21/2017
  • Est. Priority Date: 04/14/2014
  • Status: Expired due to Fees
First Claim
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1. A semiconductor device comprising:

  • a semiconductor layer;

    a plurality of unit cells formed in the semiconductor layer to each compose a transistor element that is a metal oxide semiconductor (MOS) field effect transistor element;

    a gate pad disposed on the semiconductor layer and having a shape of a circle centered on a center of the semiconductor layer as viewed in plan from a thickness direction of the semiconductor layer; and

    a main electrode pad disposed on the semiconductor layer so as to surround the gate pad and having a shape of a circular ring centered on the center of the semiconductor layer as viewed in plan, whereinthe main electrode pad is a source pad,the unit cells each have a regular hexagonal shape as viewed in plan,a source region of the unit cells other than the unit cells proximate to the gate pad is formed in a regular hexagonal ring shape as viewed in plan, and a source region of the unit cells proximate to the gate pad is formed in a partially missing regular hexagonal ring shape as viewed in plan.

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