Gate pullback at ends of high-voltage vertical transistor structure

• US 9,601,613 B2
• Filed: 07/05/2012
• Issued: 03/21/2017
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Parthasarathy, Vijay, Manley, Martin H.
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US13/541,965
• Publication Number:
  US 20120280314A1
• Time in Patent Office: 1,720 Days
• Field of Search: 257328-324, 257/488, 257/E29.26, 257/E29.262, 257/331, 257/E29.257
• US Class Current: 1/1
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A high-voltage transistor device comprising:

a plurality of transistor segments, each transistor segment being arrange on a die in an annular layout, each transistor segment including;

a pillar of semiconductor material having the annular layout with a length elongated in a first lateral direction and a width in a second lateral direction substantially orthogonal to the first lateral direction, the pillar having first and second substantially linear portions that extend in the first lateral direction and first and second rounded end portions that connect the first and second substantially linear portions at respective opposite ends, the pillar including a source region disposed at or near a surface of the pillar, a drift region that extends in a vertical direction through the die, and a body region that separates the source region from the drift region;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second gate members respectively disposed in the first and second dielectric regions at or near a top of the pillar, the first and second gate member being disposed on opposite sides of the pillar, the first and second gate members being separated from the first and second substantially linear portions of the pillar by a gate oxide having a first thickness, the first and second gate members being respectively separated from the pillar by second and third thicknesses of the gate oxide at the first and second rounded portions, the second and third thicknesses being substantially larger than the first thickness.

2. The high-voltage transistor device of claim 1 wherein the first thickness is approximately 500 Å

and the second and third thicknesses are both approximately 1 μ

m.

3. The transistor of claim 1 further comprising first and second field plates respectively disposed in the first and second dielectric regions, the first and second gate members being completely insulated from the first and second field plates.

4. The transistor of claim 1 further comprising a gate metal bus that extends in the second lateral direction orthogonal to the first lateral direction, the gate metal bus being electrically connected to the first and second gate members.

5. The high-voltage transistor of claim 1 wherein the annular layout of the pillar forma a racetrack-shaped ring or oval.

6. The high-voltage transistor of claim 1 wherein the second and third thicknesses are substantially equal.