Back power protection circuit

• US 9,601,916 B2
• Filed: 09/11/2014
• Issued: 03/21/2017
• Est. Priority Date: 09/11/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ns, Karthik, Sharma, Raghavendra Devappa, Nedalgi, Dharmaray, Bhilawadi, Prasad, Srivastava, Amit Kumar
• Primary Examiner(s): Mikels, Matthew
• Application Number:
  US14/483,649
• Publication Number:
  US 20160079747A1
• Time in Patent Office: 922 Days
• Field of Search: 235/435, 235/439, 235/441, 235/451, 235/487, 235/492
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: H02H 3/18 responsive to reversal of direct current
• CPC Class Codes: H04B 1/38 Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

Claims

1. An apparatus comprising:

one or more signal lines;

a transceiver coupled to the one or more signal lines;

a sense circuit to sense signal attributes of the one or more signal lines;

a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to the signal attributes of the one or more signal lines sensed by the sense circuit, wherein the bias generation circuit is to tri-state the transceiver by causing the transceiver to provide a high impedance;

a power-up detector to detect one or more power supplies which are provided to the transceiver; and

a circuit which is operable to select, for the transceiver, one or more bias voltages from the power-up detector or the one or more bias voltages from the bias generation circuit.

2. The apparatus of claim 1, wherein the circuit is operable to select according to presence or absence of the one or more power supplies.

3. The apparatus of claim 1, wherein the one or more signal lines are to be coupled to a device external to the apparatus.

4. The apparatus of claim 3, wherein the device is a power charger or a device to be charged for power.

5. The apparatus of claim 1, wherein the transceiver is one of:

a USB compliant transceiver;

an HDMI compliant transceiver;

or

an Interface connected to UICC element (Sim card) in NFC application.

6. The apparatus of claim 1 comprises:

a circuit which is operable to select for the transceiver one or more bias voltages from the power-up detector or the one or more bias voltages from the bias generation circuit to protect internal devices and the bias generation circuit.

7. The apparatus of claim 3, wherein the device is one of:

a USB compliant transceiver;

an HDMI compliant transceiver;

or

an Interface connected to UICC element (Sim card) in NFC application.

8. The apparatus of claim 1, wherein the transceiver includes a transmitter which is operable to provide a first voltage signaling and a second voltage signaling on the one or more signal lines.

9. The apparatus of claim 8, wherein the first voltage signaling is 1.8V signaling, and wherein the second voltage signaling is 3.3V signaling.

10. The apparatus of claim 8, wherein the transmitter comprises:

a first p-type transistor;

a second p-type transistor coupled in series with the first p-type transistor;

a first n-type transistor coupled in series with the second p-type transistor;

a second n-type transistor coupled in series with the first n-type transistor; and

a third p-type transistor coupled to the first and second n-type transistors.

11. The apparatus of claim 10, wherein the one or more bias voltages are to be received by at least two of the first p-type, second p-type, third p-type, first n-type, and second n-type transistors.