Method and apparatus for multi-rate clock generation

• US 9,602,115 B1
• Filed: 06/06/2016
• Issued: 03/21/2017
• Est. Priority Date: 06/06/2016
• Status: Active Grant

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola Solutions, Inc.
• Inventors: Rozental, Mark, Franco, Ricardo, Tordjman, Claudine, Young, Richard S.
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US15/174,871
• Time in Patent Office: 288 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H03K 5/15046 using a tapped delay line
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal

Abstract

A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.

Claims

1. A ring voltage-controlled oscillator based phase-locked loop comprising:

a delay line having a delay length extending beyond a predetermined length required for operation of the ring voltage-controlled oscillator based phase-locked loop;

a tap tuning logic circuit coupled to the delay line;

an integrated digital multi-rate clock generator coupled to the delay line;

wherein the delay line is configured to receive a tuning voltage from a loop filter of the ring voltage-controlled oscillator, the tuning voltage controls the delay line and generates a plurality of tapped output signals; and

wherein the digital multi-rate clock generator receives the plurality of tapped output signals and creates a plurality of clock signals.

2. The ring voltage-controlled oscillator based phase-locked loop of claim 1 further comprising:

a loop filter and a plurality of comparators, wherein an output signal from the loop filter is provided to the plurality of comparators and the delay line.

3. The ring voltage-controlled oscillator based phase-locked loop of claim 2, wherein the plurality of comparators compares an output signal voltage of the loop filter to a first threshold voltage and a second threshold voltage.

4. The ring voltage-controlled oscillator based phase-locked loop of claim 2, wherein the plurality of comparators are coupled to the tap tuning logic circuit and the loop filter.

5. The ring voltage-controlled oscillator based phase-locked loop of claim 1, further comprising a first divider and a second divider, wherein the first divider receives a reference clock signal from a temperature controlled crystal oscillator and the second divider receives a signal from the delay line.

6. The ring voltage-controlled oscillator based phase-locked loop of claim 5, further comprising a phase detector and a lock detector.

7. The ring voltage-controlled oscillator based phase-locked loop of claim 6, wherein the lock detector is coupled to the first divider and the second divider.

8. The ring voltage-controlled oscillator based phase-locked loop of claim 7, wherein the phase detector is coupled to the first divider, the second divider and a charge pump.

9. A method of generating a multi-rate clock signal, the method comprising:

providing a delay line for a phase-locked loop and that has a length extending beyond a predetermined length required for operation of the phase-locked loop;

receiving a tuning voltage at the delay line;

generating a plurality of tapped output signals using the delay line;

receiving at a digital multi-rate clock generator the plurality of tapped output signals from the delay line; and

combining at the digital multi-rate clock generator the plurality of tapped output signals to create one or more clock signals.

10. The method of claim 9, further comprising:

performing an initial tuning of the phase-locked loop, where performing the initial tuning includes comparing the tuning voltage to a first threshold voltage and a second threshold voltage.

11. The method of claim 10, further comprising:

adaptively adding and removing at least one delay line cell to create the one or more clock signals.