Direct metalization of electrical circuit structures

• US 9,603,249 B2
• Filed: 09/06/2012
• Issued: 03/21/2017
• Est. Priority Date: 06/02/2009
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James
• Primary Examiner(s): Vo, Peter DungBa
• Assistant Examiner(s): PARVEZ, AZM A
• Application Number:
  US14/238,638
• Publication Number:
  US 20140192498A1
• Time in Patent Office: 1,657 Days
• Field of Search: 298/25, 295/921, 298/29, 298/30, 298/31, 298/32, 298/46, 298/52, 361/767, 174/262, 216/13, 427/97.3, 438/125
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 3/4688 Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.

Claims

1. A method of making an electrical interconnect comprising the steps of:

providing a first circuitry layer comprising a first surface and a second surface;

printing at least a first dielectric layer on the first surface of the first circuitry layer to include a plurality of first recesses;

depositing a conductive material on surfaces of a plurality of the first recesses comprising a plurality of first conductive structures electrically coupled to, and extending perpendicular to, the first circuitry layer;

printing a filler material in the first conductive structures;

printing at least a second dielectric layer on the first dielectric layer to include a plurality of second recesses at least partially aligned with a plurality of the first conductive structures;

depositing a conductive material on surfaces of a plurality of the second recesses comprising a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures; and

printing a dielectric material in one or more of the first and second recesses to surround one or more of the first and second conductive structures.

2. The method of claim 1 comprising electrically coupling contact pads on an IC device to a plurality of the second conductive structures.

3. The method of claim 1 comprising the steps of:

locating a second circuitry layer on the second dielectric layer to electrically couple the second circuitry layer with a plurality of the second conductive structures; and

printing at least a third dielectric layer on the second dielectric layer to include a plurality of third recesses at least partially aligned with a plurality of the second conductive structures.

4. The method of claim 3 comprising etching away portions of the second circuitry layer located in the third recesses to expose a plurality of the second conductive structures.

5. The method of claim 3 comprising the steps of:

plating a conductive material on surfaces of a plurality of the third recesses comprising a plurality of third conductive structures electrically coupled to, and extending parallel to the second conductive structures; and

electrically coupling contact pads on an IC device to a plurality of the third conductive structures, wherein the step of electrically coupling comprises one of a flip chip attachment directly to a plurality of third conductive structures, solder balls, or wire bonding.

6. The method of claim 3 comprising the steps of:

locating a third circuitry layer on the third dielectric layer; and

attaching a covering layer to the third circuitry layer, the covering layer comprising a plurality of openings exposing contact pads on the third circuitry layer configured to electrically couple with an IC device.

7. The method of claim 1 comprising attaching a covering layer to the second surface of the first circuitry layer, the covering layer comprising a plurality of openings exposing a plurality of contact pads on the first circuitry layer adapted to electrically couple with a PCB.

8. The method of claim 1 wherein at least one of the first and second conductive structures comprise a coaxial conductive structure.

9. The method of claim 1 comprising printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layer.