Integrated device for temporal binning of received photons

• US 9,606,058 B2
• Filed: 09/09/2016
• Issued: 03/28/2017
• Est. Priority Date: 08/08/2014
• Status: Active Grant

• Current Assignee: Quantum-Si Incorporated
• Original Assignee: Quantum-Si Incorporated
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Boisvert, David
• Primary Examiner(s): Porta, David
• Assistant Examiner(s): BOOSALIS, FANI POLYZOS
• Application Number:
  US15/261,697
• Publication Number:
  US 20160377543A1
• Time in Patent Office: 200 Days
• US Class Current: 1/1
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01N 2021/6439 with indicators, stains, dyes, tags, labels, marks
• CPC Class Codes: G01N 2021/6441 with two or more labels
• CPC Class Codes: G01N 21/6408 with measurement of decay time, time resolved fluorescence
• CPC Class Codes: G01N 21/6428 Measuring fluorescence of fluorescent products of reactions or of fluorochrome labelled reactive substances, e.g. measuring quenching effects, using measuring "optrodes" in vivo A61B5/00; immunoassay G01N33/53
• CPC Class Codes: G01N 21/645 Specially adapted constructive features of fluorimeters
• CPC Class Codes: G01N 21/6458 Fluorescence microscopy fluorescence microscopes per se G02B21/0076 and G02B21/16
• CPC Class Codes: G01N 2201/06113 Coherent sources; lasers
• CPC Class Codes: G01N 2201/0697 Pulsed lasers
• CPC Class Codes: G01S 17/894 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: G01S 7/4865 Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak peak detection in noise, signal conditioning G01S7/487
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes

Abstract

An integrated circuit includes a photodetection region configured to receive incident photons. The photodetection region is configured to produce a plurality of charge carriers in response to the incident photons. The integrated circuit also includes at least one charge carrier storage region. The integrated circuit also includes a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into the at least one charge carrier storage region based upon times at which the charge carriers are produced.

Claims

1. An integrated circuit, comprising:

a plurality of pixels, a first pixel of the plurality of pixels comprising;

a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons;

a plurality of charge carrier storage regions; and

a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into respective charge carrier storage regions of the plurality of charge carrier storage regions based upon times at which the charge carriers are produced, and to aggregate, in the plurality of charge carrier storage regions, charge carriers produced in a plurality of measurement periods; and

a readout circuit configured to read out signals from the plurality of charge carrier storage regions,

wherein the plurality of measurement periods comprises at least one million measurement periods.

2. The integrated circuit of claim 1, wherein a duration of the plurality of measurement periods is less than 50 milliseconds.

3. The integrated circuit of claim 2, wherein the duration of the plurality of measurement periods is greater than one millisecond.

4. The integrated circuit of claim 1, wherein the first pixel is configured to time-bin arrival of single photons.

5. The integrated circuit of claim 1, wherein the plurality of charge carrier storage regions correspond to time bins.

6. The integrated circuit of claim 1, wherein individual measurement periods of the plurality of measurement periods have a timing based on a timing of excitation light pulses.

7. The integrated circuit of claim 1, wherein individual measurement periods of the plurality of measurement periods include:

a first period of time in which charge carriers produced from photons of an excitation light pulse are discarded; and

a second period of time in which a charge carrier is selectively directed to a charge carrier storage region of the plurality of charge carrier storage regions.

8. The integrated circuit of claim 1, wherein the first pixel is configured to measure and/or discriminate a luminance lifetime to sequence a nucleic acid.

9. An integrated circuit, comprising:

a plurality of pixels, a first pixel of the plurality of pixels comprising;

a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons;

a plurality of charge carrier storage regions; and

a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into respective charge carrier storage regions of the plurality of charge carrier storage regions based upon times at which the charge carriers are produced, and to aggregate, in the plurality of charge carrier storage regions, charge carriers produced in a plurality of measurement periods; and

a readout circuit configured to read out signals from the plurality of charge carrier storage regions,

wherein individual measurement periods of the plurality of measurement periods have a timing based on a timing of excitation light pulses.

10. The integrated circuit of claim 9, wherein the charge carrier segregation structure comprises a plurality of electrodes.

11. The integrated circuit of claim 10, further comprising a control circuit configured to direct the charge carriers into the respective charge carrier storage regions by changing a voltage of one or more electrodes of the plurality of electrodes.

12. The integrated circuit of claim 10, wherein the plurality of the electrodes is configured to establish an electric potential gradient.

13. The integrated circuit of claim 9, wherein the photodetection region and the plurality of charge carrier storage regions comprise a semiconductor material.

14. The integrated circuit of claim 9, wherein a second pixel of the plurality of pixels comprises:

a second photodetection region configured to produce a second plurality of charge carriers in response to second incident photons;

a second plurality of charge carrier storage regions; and

a second charge carrier segregation structure configured to selectively direct second charge carriers of the second plurality of charge carriers into respective second charge carrier storage regions of the second plurality of charge carrier storage regions based upon times at which the second charge carriers are produced, and to aggregate, in the second plurality of charge carrier storage regions, second charge carriers produced in the plurality of measurement periods.

15. The integrated circuit of claim 9, wherein the plurality of measurement periods comprises at least one thousand measurement periods.

16. The integrated circuit of claim 9, further comprising a control circuit configured to control the charge carrier segregation structure to discard the charge carriers produced from photons of the excitation light pulses.

17. The integrated circuit of claim 9, wherein the first pixel is configured to time-bin arrival of single photons.

18. The integrated circuit of claim 9, wherein the plurality of charge carrier storage regions correspond to time bins.

19. The integrated circuit of claim 9, wherein a quantity of the plurality of charge carrier storage regions is two.

20. The integrated circuit of claim 9, wherein the first pixel is configured to measure and/or discriminate a luminance lifetime to sequence a nucleic acid.

21. The integrated circuit of claim 9,

wherein the first pixel is configured to time-bin arrival of single photons,

wherein the plurality of charge carrier storage regions correspond to time bins, and

wherein individual measurement periods of the plurality of measurement periods include:

a first period of time in which charge carriers produced from photons of an excitation light pulse are discarded; and

a second period of time in which a charge carrier is selectively directed to a charge carrier storage region of the plurality of charge carrier storage regions.

22. An integrated circuit, comprising:

a plurality of pixels, a first pixel of the plurality of pixels comprising;

a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons;

a plurality of charge carrier storage regions; and

a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into respective charge carrier storage regions of the plurality of charge carrier storage regions based upon times at which the charge carriers are produced, and to aggregate, in the plurality of charge carrier storage regions, charge carriers produced in a plurality of measurement periods; and

a readout circuit configured to read out signals from the plurality of charge carrier storage regions,

wherein individual measurement periods of the plurality of measurement periods include;

a first period of time in which charge carriers produced from photons of an excitation light pulse are discarded; and

a second period of time in which a charge carrier is selectively directed to a charge carrier storage region of the plurality of charge carrier storage regions.

23. The integrated circuit of claim 22, wherein the first pixel is configured to time-bin arrival of single photons.

24. The integrated circuit of claim 22, wherein the plurality of charge carrier storage regions correspond to time bins.

25. The integrated circuit of claim 22, wherein the first pixel is configured to measure and/or discriminate a luminance lifetime to sequence a nucleic acid.

26. An integrated circuit, comprising:

a plurality of pixels, a first pixel of the plurality of pixels comprising;

a photodetection region configured to receive incident photons, the photodetection region being configured to produce a plurality of charge carriers in response to the incident photons;

a plurality of charge carrier storage regions; and

a charge carrier segregation structure configured to selectively direct charge carriers of the plurality of charge carriers into respective charge carrier storage regions of the plurality of charge carrier storage regions based upon times at which the charge carriers are produced, and to aggregate, in the plurality of charge carrier storage regions, charge carriers produced in a plurality of measurement periods; and

a readout circuit configured to read out signals from the plurality of charge carrier storage regions,

wherein the plurality of charge carrier storage regions correspond to time bins.

27. The integrated circuit of claim 26, wherein the first pixel is configured to time-bin arrival of single photons.

28. The integrated circuit of claim 26, further comprising a control circuit configured to control the charge carrier segregation structure to change a timing, duration and/or number of the time bins.

29. The integrated circuit of claim 26, wherein the time bins have nanosecond or picosecond resolution.

30. The integrated circuit of claim 26, wherein the first pixel is configured to measure and/or discriminate a luminance lifetime to sequence a nucleic acid.