Method and apparatus for asynchronous processor based on clock delay adjustment

• US 9,606,801 B2
• Filed: 09/08/2014
• Issued: 03/28/2017
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Tong, Wen, Ge, Yiqun, Zhang, Qifan, Shi, Wuxian, Huang, Tao
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US14/480,531
• Publication Number:
  US 20150074446A1
• Time in Patent Office: 932 Days
• Field of Search: 713/1
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 2009/3883 Two-engine architectures, i.e. stand-alone processor acting as a slave processor
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Claims

1. An asynchronous processing system, comprising:

an asynchronous logic circuit configured to perform at least one processing function on input data;

a controller configured to;

identify from the at least one processing function, a type of processing to be performed by the asynchronous logic circuitry pursuant to the at least one processing function;

determine from the identified type of processing, a processing delay period of time; and

provide the processing delay period of time to a self-clocked generator coupled to the asynchronous logic circuit;

the self-clocked generator configured to receive a trigger signal and output a self-clocking signal the processing delay period of time after receiving the trigger signal, wherein the processing delay period of time is configurable; and

a data storage element configured to store processed data from the asynchronous logic circuit in response to the self-clocking signal.

2. The asynchronous processing system in accordance with claim 1 wherein the processing delay period of time is programmable within a range, wherein the range ensures sufficient time for completion of the processing function of the asynchronous logic circuit.

3. The asynchronous processing system in accordance with claim 1 wherein the processing delay period of time is selected from at least two possible different periods of time.

4. The asynchronous processing system in accordance with claim 3 wherein the processing delay period of time is selected in response to a processing instruction.

5. The asynchronous processing system in accordance with claim 4 wherein the processing delay period of time is selected based on an opcode associated with the processing instruction.

6. The asynchronous processing system in accordance with claim 1 further comprising:

a second asynchronous logic circuit configured to perform at least one processing function on input data;

a second self-clocked generator coupled to the second asynchronous logic circuit and configured to receive a second trigger signal and output a second self-clocking signal within a second processing delay period of time after receiving the second trigger signal, wherein the second processing delay period of time is configurable; and

a second data storage element configured to store processed data from the second asynchronous logic circuit in response to the second self-clocking signal.

7. The asynchronous processing system in accordance with claim 1 wherein the asynchronous logic circuit comprises an arithmetic logic unit (ALU).

8. A method for operating an asynchronous processing system comprising asynchronous logic circuitry, the method comprising:

receiving a first processing instruction;

identifying from the first processing instruction a first type of processing to be performed by the asynchronous logic circuitry pursuant to the first processing instruction;

determining from the identified first type of processing, a first processing delay period of time; and

configuring a self-clock generator coupled to the asynchronous logic circuitry to output a self-clocking signal after receiving a trigger signal in accordance with the determined first processing delay period of time.

9. The method in accordance with claim 8 further comprising:

processing, by the asynchronous logic circuitry, input data to generate processed output data; and

storing the processed output data in memory in response to the self-clocking signal.

10. The method in accordance with claim 9 wherein the memory is a data latch, and the method further comprises:

latching the processed output data into the data latch in response to the self-clocking signal.

11. The method in accordance with claim 8 further comprising:

processing, by the asynchronous logic circuitry, input data to generate processed output data in accordance with the first type of processing and the first processing instruction;

receiving a second processing instruction;

identifying from the second processing instruction a second type of processing to be performed by the asynchronous logic circuitry pursuant to the second processing instruction;

determining from the identified second type of processing, a second processing delay period of time; and

configuring the self-clock generator coupled to the asynchronous logic circuitry to output another self-clocking signal after receiving another trigger signal in accordance with the determined second processing delay period of time.

12. The method in accordance with claim 11 wherein the first processing instruction is an adding instruction and the second processing instruction is a multiplication function, and wherein the first processing delay period of time is less than the second processing delay period of time.

13. The method in accordance with claim 8 wherein the asynchronous logic circuitry comprises an arithmetic logic unit (ALU).

14. The method in accordance with claim 8

wherein identifying from the first processing instruction the first type of processing to be performed by the asynchronous logic circuitry comprises:

at least partially decoding the processing instruction to determine an opcode.