System for pre-fetching data frames using hints from work queue scheduler

• US 9,606,926 B2
• Filed: 11/29/2014
• Issued: 03/28/2017
• Est. Priority Date: 11/29/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Garg, Vakul, Bhushan, Bharat
• Primary Examiner(s): Mackall, Larry T
• Application Number:
  US14/556,143
• Publication Number:
  US 20160154737A1
• Time in Patent Office: 850 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions

Abstract

A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

Claims

1. A system for pre-fetching a data frame from a system memory, comprising:

a data processing module for generating a de-queue request associated with the data frame;

a queue manager connected to the data processing module for receiving the de-queue request, storing a frame queue that includes a frame descriptor associated with the data frame, identifying the frame descriptor based on the de-queue request, and generating a pre-fetch hint signal;

a pre-fetch manager connected to the queue manager for receiving the pre-fetch hint signal and generating a pre-fetch signal; and

a cache memory connected to the pre-fetch manager for receiving the pre-fetch signal and connected to the system memory for pre-fetching the data frame based on the pre-fetch signal,

wherein the queue manager further de-queues the frame descriptor from the frame queue and provides the frame descriptor to the data processing module subsequent to storing the first data frame in the cache memory, and the data processing module fetches the data frame from the cache memory based on the frame descriptor received from the queue manager.

2. The system of claim 1, wherein a pre-fetch attribute is associated with at least one of the frame queue and the frame descriptor and indicates a pre-fetch characteristic of the data frame corresponding to the frame descriptor included in the frame queue.

3. The system of claim 2, wherein the queue manager generates the pre-fetch hint signal based on the pre-fetch characteristic of the data frame.

4. The system of claim 3, wherein the frame descriptor includes a data frame address field that stores an address of the data frame and a data frame length field that indicates a size of the data frame, and wherein the pre-fetch hint signal includes information indicative of the address and the size of the data frame.

5. The system of claim 1, further comprising a pre-fetch request queue connected to the queue manager for receiving the pre-fetch hint signal, storing the pre-fetch hint signal, and transmitting the pre-fetch hint signal to the pre-fetch manager.

6. The system of claim 1, wherein the system memory further stores a plurality of data frames.

7. The system of claim 6, wherein the queue manager further stores a plurality of frame queues, and wherein each frame queue includes a plurality of frame descriptors, and wherein each frame descriptor is associated with a corresponding data frame of the plurality of data frames.

8. The system of claim 1, wherein the data processing module comprises at least one of a hardware accelerator, a processor core, a co-processor, an application-specific integrated circuit, and a control unit.

9. A method for pre-fetching a plurality of data frames in a system that includes a data processing module, a pre-fetch manager, a cache memory, a system memory that stores the plurality of data frames, and a queue manager that stores a plurality of frame queues, wherein each frame queue includes a plurality of frame descriptors, and wherein each frame descriptor is associated with a corresponding data frame of the plurality of data frames, the method comprising:

receiving a de-queue request associated with a first data frame of the plurality of data frames;

identifying a first frame queue of the plurality of frame queues based on the de-queue request;

identifying a first frame descriptor of the plurality of frame descriptors of the first frame queue based on the de-queue request, wherein the first frame descriptor is associated with the first data frame;

generating a pre-fetch hint signal;

generating a pre-fetch signal based on the pre-fetch hint signal;

pre-fetching the first data frame from the system memory to the cache memory based on the pre-fetch signal;

de-queuing the first frame descriptor from the first frame queue and providing the first frame descriptor to the data processing module subsequent to storing the first data frame in the cache memory; and

fetching the first data frame from the cache memory to the data processing module based on the frame descriptor received by the data processing module.

10. The method of claim 9, wherein a pre-fetch attribute is associated with at least one of the first frame queue and the first frame descriptor and indicates a pre-fetch characteristic of the first data frame corresponding to the first frame descriptor of the first frame queue.

11. The method of claim 10, further comprising generating the pre-fetch hint signal based on the pre-fetch characteristic of the first data frame, wherein the pre-fetch hint signal includes information indicative of address and size of the first data frame.

12. An integrated circuit, comprising:

a system memory for storing a plurality of data frames;

an internal memory for storing a plurality of frame queues, wherein each frame queue includes a plurality of frame descriptors, and wherein each frame descriptor is associated with a corresponding data frame of the plurality of data frames;

a data processing module for generating a de-queue request associated with a first data frame of the plurality of data frames;

a de-queuing module connected to the data processing module for receiving the de-queue request and the internal memory, identifying a first frame queue of the plurality of frame queues based on the de-queue request, identifying a first frame descriptor of the plurality of frame descriptors of the first frame queue, and generating a pre-fetch hint signal, wherein the first frame descriptor is associated with the first data frame;

a pre-fetch manager connected to the de-queuing module for receiving the pre-fetch hint signal and generating a pre-fetch signal; and

a cache memory connected to the pre-fetch manager for receiving the pre-fetch signal and the system memory for pre-fetching the first data frame from the system memory based on the pre-fetch signal,

wherein the de-queuing module further de-queues the first frame descriptor from the first frame queue and provides the first frame descriptor to the data processing module subsequent to storing the first data frame in the cache memory, and the data processing module fetches the first data frame from the cache memory based on the first frame descriptor received from the de-queuing module.

13. The integrated circuit of claim 12, wherein a pre-fetch attribute is associated with at least one of the first frame queue and the first frame descriptor and indicates a pre-fetch characteristic of the first data frame corresponding to the first frame descriptor of the first frame queue.

14. The integrated circuit of claim 13, wherein the queue manager generates the pre-fetch hint signal based on the pre-fetch characteristic of the first data frame, and wherein the pre-fetch hint signal includes information indicative of address and size of the first data frame.