Memory system

• US 9,606,928 B2
• Filed: 02/24/2015
• Issued: 03/28/2017
• Est. Priority Date: 08/26/2014
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Eguchi, Yasuyuki
• Primary Examiner(s): McMahon, Daniel
• Application Number:
  US14/630,444
• Publication Number:
  US 20160062896A1
• Time in Patent Office: 763 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system includes: a memory controller which executes a data access process with an external device using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.

Claims

1. A memory system comprising:

a memory controller which executes a data access process with an external device using an access unit;

a first memory which is connected to the memory controller via a first bus and which has a first latency; and

a second memory which is connected to the memory controller via a second bus and which has a second latency longer than the first latency;

wherein the access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory, and

the memory controller executes a first data access process with the first memory using the first access size, and executes a second data access process with the second memory using the second access size.

2. The system of claim 1, wherein the second access size is larger than the first access size.

3. The system of claim 1, wherein the first access size is set based on the second latency.

4. The system of claim 1, wherein the first access size is set such that the first memory completes the first data access process in the second latency.

5. The system of claim 1, wherein the memory controller includes a register which stores information of the first access size and information of the second access size.

6. The system of claim 1, wherein

the first memory includes a first register which stores information of the first access size, and

the second memory includes a second register which stores information of the second access size.

7. The system of claim 6, wherein

the second register further stores information of the first access size, and

the second memory includes a control circuit which controls a timing when data is received from the second bus and a timing when data is output to the second bus, using the information of the first access size and the first latency.

8. The system of claim 7, wherein the control circuit counts a clock based on the first access size and controls the timings in accordance with the count result.

9. The system of claim 1, wherein

the first memory includes a memory cell array and a control circuit which accesses the memory cell array, and

the control circuit receives an address from the memory controller, increments the address based on the first access size, and accesses the memory cell array using the incremented address.

10. The system of claim 1, wherein the first memory includes a buffer which stores write data with the second access size written to the second memory.

11. The system of claim 10, wherein the first memory includes a control circuit which writes the write data with the second access size to the buffer after write data with the first access size is received.

12. The system of claim 11, wherein in a case where sudden power loss occurs before writing to the second memory is completed, the memory controller transfers the write data stored in the buffer to the second memory after the power returns.

13. The system of claim 1, wherein the memory controller includes a first error checking and correcting (ECC) circuit which performs error correction on the first access size and a second ECC circuit which performs error correction on the second access size.

14. The system of claim 13, wherein the second ECC circuit has a higher correction capability than the first ECC circuit.

15. The system of claim 1, wherein the first bus and the second bus are shared as a common bus.

16. The system of claim 1, wherein

the access unit comprises a data body and management information on the data body,

data of the first access size is the management information, and

data of the second access size is the data body.

17. The system of claim 1, wherein

the first memory is a magnetic random access memory (MRAM), and

the second memory is a NAND flash memory.

18. The system of claim 1, wherein

the memory controller receives write data from the external device, the write data including a first data portion and a second data portion, the first data portion having the first access size, and the second data portion having the second access size, and

the memory controller writes the first data portion to the first memory and writes the second data portion to the second memory.

19. The system of claim 1, wherein

read data includes a first data portion and a second data portion, the first data portion having the first access size, and the second data portion having the second access size,

the memory controller reads the first data portion from the first memory and reads the second data portion from the second memory, and

the memory controller sends the read data to the external device.

20. The system of claim 1, wherein

the first memory comprises a nonvolatile memory, and

the second memory comprises a nonvolatile memory.