Methods for sharing bandwidth across a packetized bus and systems thereof
First Claim
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1. A method for sharing bus bandwidth, the method comprising:
- segmenting by a network traffic management device a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets;
accessing by the network traffic management device and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and
alternately transmitting by the network traffic management device the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets.
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Abstract
A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus.
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Citations
18 Claims
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1. A method for sharing bus bandwidth, the method comprising:
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segmenting by a network traffic management device a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets; accessing by the network traffic management device and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and alternately transmitting by the network traffic management device the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A network traffic management device, comprising memory comprising programmed instructions stored in the memory and one or more processors configured to be capable of executing the programmed instructions stored in the memory to:
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segment the a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets; access and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and alternately transmit the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A non-transitory computer readable medium having stored thereon instructions for facilitating cipher selection comprising executable code which when executed by one or more processors, causes the processors to perform steps comprising:
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segmenting the a first read request packet received from a first direct memory access (DMA) channel into one or more first constituent central processing unit (CPU) bus read request packets and a second read request packet received from a second DMA channel into one or more second constituent CPU bus read request packets; accessing and from a memory coupled to a packetized CPU bus one or more first constituent CPU bus read completion packets corresponding to the one or more first constituent CPU bus read request packets and one or more second constituent CPU bus read completion packets corresponding to the one or more second constituent CPU bus read request packets; and alternately transmitting the one or more first constituent CPU bus read completion packets of the first DMA channel and the one or more second constituent CPU bus read completion packets of the second DMA channel across a packetized CPU bus, wherein one or more of the first constituent CPU bus read completion packets comprises a same size as one or more of the second constituent CPU bus read completion packets. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification