Display apparatus and display panel driver including software-controlled gate waveforms

• US 9,607,566 B2
• Filed: 03/28/2014
• Issued: 03/28/2017
• Est. Priority Date: 04/01/2013
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Inventors: Saito, Satoshi, Kitamura, Kota, Tanabe, Hajime
• Primary Examiner(s): Balaoing, Ariel
• Assistant Examiner(s): Ritchie, Darlene M
• Application Number:
  US14/229,657
• Publication Number:
  US 20140313115A1
• Time in Patent Office: 1,096 Days
• US Class Current: 1/1
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A liquid crystal display apparatus includes a liquid crystal display panel having gate lines and source lines, a GIP circuit which drives the gate lines and a source driver IC3 which drives the source lines. The source driver IC3 includes a gate control signal generator which generates gate control signals SOUT1-SOUTn which control the GIP circuit. The gate control signal generator is configured so that it is possible to control the waveforms of the gate control signals SOUT1-SOUTn in software.

Claims

1. A display apparatus, comprising:

a display panel comprising gate lines and source lines;

a gate driver configured to drive each of the gate lines; and

a source driver configured to drive each of the source lines,

wherein said source driver comprises a gate control signal generator configured to generate a gate control signal to control said gate driver,

wherein said gate control signal generator comprises;

a waveform control register;

an internal digital signal generator configured to generate a plurality of multi-level internal digital signals, whose waveforms are different from each other, in response to a first register value held by said waveform control register, each of the multi-level internal digital signals including a 3-valued or more digital signal;

a pulse swap circuit configured to output an internal gate control signal generated from the plurality of multi-level internal digital signals, the internal gate control signal including a digital signal; and

a level shifter connected between the gate driver and the pulse swap circuit and configured to perform a level shift on the internal gate control signal to generate the gate control signal, and

wherein said pulse swap circuit is responsive to a second register value held by said waveform control register for outputting as the internal gate control signal a signal selected from the plurality of multi-level internal digital signals or a signal generated by performing a logical operation on a plurality of signals selected from internal digital signals including the plurality of multi-level internal digital signals.

2. The display apparatus according to claim 1, wherein a period and phase of each of the plurality of multi-level internal digital signals are adjusted based on the first register value held by said waveform control register.

3. A display apparatus, comprising:

a display panel comprising gate lines and source lines;

a gate driver configured to drive each of the gate lines; and

a source driver configured to drive each of the source lines,

wherein said source driver comprises a gate control signal generator configured to generate a gate control signal to control said gate driver,

wherein said gate control signal generator is configured to allow a waveform of the gate control signal to be controlled by software,

wherein said gate control signal generator comprises;

a waveform control register;

a first internal digital signal generator configured to generate a plurality of internal digital signals, whose waveforms are different from each other, in response to a first register value held by said waveform control register;

a second internal digital signal generator configured to generate a plurality of multi-level internal digital signals different in waveform from each other in response to a second register value held by said waveform control register;

a pulse swap circuit configured to output an internal gate control signal generated from the plurality of internal digital signals and the plurality of multi-level internal digital signals; and

a level shifter configured to perform a level shift on the internal gate control signal to generate the gate control signal,

wherein said pulse swap circuit is responsive to a third register value held by said waveform control register for outputting as the internal gate control signal a signal selected from the plurality of internal digital signals and the plurality of multi-level internal digital signals or a signal generated by performing a logical operation on a plurality of signals selected from the plurality of internal digital signals and the plurality of multi-level internal digital signals.

4. A display panel driver, comprising:

a source driver circuit section configured to drive source lines of a display panel; and

a gate control signal generating section configured to generate a gate control signal to control a gate driver which drives a gate line of said display panel,

wherein said gate control signal generator comprises;

a waveform control register;

an internal digital signal generator configured to generate a plurality of multi-level internal digital signals, whose waveforms are different from each other, in response to a first register value held by said waveform control register, each of the multi-level internal digital signals including a 3-valued or more digital signal;

a pulse swap circuit configured to output an internal gate control signal generated from the plurality of multi-level internal digital signals, the internal gate control signal being a digital signal; and

a level shifter connected between the gate driver and the pulse swap circuit and configured to perform a level shift on the internal gate control signal to generate the gate control signal, and

wherein said pulse swap circuit is responsive to a second register value held by said waveform control register for outputting as the internal gate control signal a signal selected from the plurality of multi-level internal digital signals or a signal generated by performing a logical operation on a plurality of signals selected from the plurality of multi-level internal digital signals.

5. The display panel driver according to claim 4, wherein a period and a phase of each of the plurality of multi-level internal digital signals are controlled based on the first register value held by said corrugated control register.

6. A display panel driver, comprising:

a source driver circuit section configured to drive source lines of a display panel; and

a gate control signal generating section configured to generate a gate control signal to control a gate driver which drives a gate line of said display panel,

wherein said gate control signal generating section is configured to be able to control a waveform of the gate control signal by software,

wherein said gate control signal generator comprises;

a waveform control register;

a first internal digital signal generator configured to generate a plurality of internal digital signals different in waveform from each other in response to a first register value held by said waveform control register;

a second internal digital signal generator configured to generate a plurality of multi-level internal digital signals different in waveform from each other in response to a second register value held by said waveform control register,

a pulse swap circuit configured to output an internal gate control signal generated from the plurality of internal digital signals and the plurality of multi-level internal digital signals; and

a level shifter configured to perform the internal gate control signal on a level shift to generate the gate control signal,

wherein said pulse swap circuit is responsive for a third register value held by said waveform control register for outputting as the internal gate control signal a signal selected from the plurality of internal digital signals and the plurality of multi-level internal digital signals, or a signal generated by performing a logic operation of a plurality of signals selected from the plurality of internal digital signals and the plurality of multi-level internal digital signals.