Non-volatile dynamic random access memory (NVDRAM) with programming line

• US 9,607,663 B2
• Filed: 08/11/2015
• Issued: 03/28/2017
• Est. Priority Date: 08/11/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Roy, Anirban, Sadd, Michael A.
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US14/823,698
• Publication Number:
  US 20170047098A1
• Time in Patent Office: 595 Days
• Field of Search: 365/72
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

A memory circuit includes a first bit line, a second bit line, and a memory cell that is coupled to first bit line and the second bit line. The memory cell includes a capacitor, a first pass gate transistor, a non-volatile (NV) element, and a second pass gate transistor. The first capacitor has a first terminal coupled to a first storage node and a second terminal coupled to a reference. The first pass gate transistor is coupled between the first bit line and the first storage node. The NV element and a second pass gate transistor are coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line.

Claims

1. A memory circuit, comprising:

a first bit line;

a first program line;

a first memory cell, coupled to the first bit line and the first program line, comprising;

a first capacitor having a first terminal coupled to a first storage node and a second terminal coupled to a reference;

a first pass gate transistor coupled between the first bit line and the first storage node; and

a first non-volatile (NV) element and a second pass gate transistor coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line; and

a programming transistor having a first current electrode coupled to a second program line, a control electrode coupled to a word line, and a second current electrode coupled to a programming node between the second pass gate transistor and the NV element.

2. The memory circuit of claim 1, further comprising:

column circuitry coupled to the first bit line that senses a logic state based on charge stored at the first storage node in a first mode and based on a resistance of the first NV element in a second mode.

3. The memory circuit of claim 2, wherein the second pass gate transistor couples the second terminal of the first NV element to the first program line in the second mode.

4. The memory circuit of claim 3, wherein the second pass gate transistor decouples the second terminal of the first NV element from the first program line in the first mode.

5. The memory of claim 2, wherein, in the second mode, the programming transistor couples the second terminal of the first NV element to the first program line for a predetermined time while the second pass gate transistor is disabled.

6. The memory circuit of claim 2, wherein the control circuitry detects, in the first mode, a logic state of the first memory cell a predetermined time after the first pass gate transistor couples the first storage node to the first bit line.

7. The memory circuit of claim 2, wherein the first NV element is programmed to a first logic state by passing current from the first bit line to the first program line through the first pass gate transistor, the second pass gate transistor, and the NV element.

8. The memory circuit of claim 7, wherein the first NV element is programmed to a second logic state by passing current from the first program line to the first bit line through the first pass gate transistor, the second pass gate transistor, and the NV element.

9. The memory circuit of claim 1, wherein a programming current passes between the second program line and the first program line through the programming transistor and the NV element.

10. A method of operating a memory circuit having a first memory cell having a capacitor and a non-volatile (NV) element, wherein the first memory cell is coupled to a first bit line and a first program line, comprising:

programming the first memory cell by selectively applying current between the first program line and through the NV element to establish a logic state of the NV element;

writing the first memory cell by applying a voltage to the first bit line while coupling the first bit line to the capacitor to store charge based on the voltage in the capacitor; and

restoring the logic state of the NV element to the first memory cell by drawing current between the NV element and the first program line for a predetermined time.

11. The method of claim 10, further comprising:

reading a logic state of the first memory cell by coupling the first bit line to the capacitor and decoupling the first program line from the NV element.

12. The method of claim 11, wherein the coupling the first bit line to the capacitor comprises enabling a first pass gate transistor that is coupled between the capacitor and the first bit line.

13. The method of claim 10, wherein the reading the logic state of the first memory cell further comprises using control circuitry coupled to the first bit line.

14. The method of claim 13, further comprising storing data in the first memory cell by selecting the current for programming the NV element based on the logic state read by the control circuitry.

15. The method of claim 10, wherein programming is further characterized as passing current between the first bit line and the first program line through the NV element.

16. The method of claim 10, wherein the memory circuit further comprises a second program line, wherein programming is further characterized as passing current between the first and second program lines through the NV element.

17. A memory circuit, comprising:

a first bit line;

a first program line;

a first memory cell, coupled to the first bit line and the first program line, comprising;

a first DRAM cell coupled to the first bit line, wherein the first DRAM cell has a storage node; and

a first non-volatile (NV) element and a pass gate transistor coupled in series, wherein the first NV element and the pass gate transistor are coupled between the storage node and the first program line; and

a programming transistor coupled between a programming node between the pass gate transistor and the first NV element and a second program line wherein programming of the NV element occurs by passing current between the first and second program lines;

wherein, in a restore mode of the memory circuit, current is drawn through the first NV element for a predetermined time.

18. The memory circuit of claim 17, wherein programming of the NV element occurs by passing current between the first bit line and the first program line through the NV element.