Non-volatile dynamic random access memory (NVDRAM) with programming line
First Claim
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1. A memory circuit, comprising:
- a first bit line;
a first program line;
a first memory cell, coupled to the first bit line and the first program line, comprising;
a first capacitor having a first terminal coupled to a first storage node and a second terminal coupled to a reference;
a first pass gate transistor coupled between the first bit line and the first storage node; and
a first non-volatile (NV) element and a second pass gate transistor coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line; and
a programming transistor having a first current electrode coupled to a second program line, a control electrode coupled to a word line, and a second current electrode coupled to a programming node between the second pass gate transistor and the NV element.
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Abstract
A memory circuit includes a first bit line, a second bit line, and a memory cell that is coupled to first bit line and the second bit line. The memory cell includes a capacitor, a first pass gate transistor, a non-volatile (NV) element, and a second pass gate transistor. The first capacitor has a first terminal coupled to a first storage node and a second terminal coupled to a reference. The first pass gate transistor is coupled between the first bit line and the first storage node. The NV element and a second pass gate transistor are coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line.
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Citations
18 Claims
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1. A memory circuit, comprising:
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a first bit line; a first program line; a first memory cell, coupled to the first bit line and the first program line, comprising; a first capacitor having a first terminal coupled to a first storage node and a second terminal coupled to a reference; a first pass gate transistor coupled between the first bit line and the first storage node; and a first non-volatile (NV) element and a second pass gate transistor coupled in series, wherein the first NV element and the second pass gate transistor are coupled between the first storage node and the first program line; and a programming transistor having a first current electrode coupled to a second program line, a control electrode coupled to a word line, and a second current electrode coupled to a programming node between the second pass gate transistor and the NV element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of operating a memory circuit having a first memory cell having a capacitor and a non-volatile (NV) element, wherein the first memory cell is coupled to a first bit line and a first program line, comprising:
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programming the first memory cell by selectively applying current between the first program line and through the NV element to establish a logic state of the NV element; writing the first memory cell by applying a voltage to the first bit line while coupling the first bit line to the capacitor to store charge based on the voltage in the capacitor; and restoring the logic state of the NV element to the first memory cell by drawing current between the NV element and the first program line for a predetermined time. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A memory circuit, comprising:
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a first bit line; a first program line; a first memory cell, coupled to the first bit line and the first program line, comprising; a first DRAM cell coupled to the first bit line, wherein the first DRAM cell has a storage node; and a first non-volatile (NV) element and a pass gate transistor coupled in series, wherein the first NV element and the pass gate transistor are coupled between the storage node and the first program line; and a programming transistor coupled between a programming node between the pass gate transistor and the first NV element and a second program line wherein programming of the NV element occurs by passing current between the first and second program lines; wherein, in a restore mode of the memory circuit, current is drawn through the first NV element for a predetermined time. - View Dependent Claims (18)
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Specification