Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication

• US 9,607,673 B1
• Filed: 12/18/2015
• Issued: 03/28/2017
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Fox, John, Holden, Brian, Shokrollahi, Amin, Singh, Anant, Surace, Giuseppe
• Primary Examiner(s): Abad, Farley
• Application Number:
  US14/974,698
• Time in Patent Office: 466 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Claims

1. An apparatus comprising:

a physical layer signaling protocol control circuit configured to receive consecutive codewords of a vector signaling code, each codeword represented as a set of symbols received synchronously over a collection of interconnection signal lines, the consecutively received codewords collectively representing an encoded message packet, the physical layer signaling protocol control circuit configured to decode the symbols of each consecutively received codeword into consecutive sets of data bits, and to form a set of link layer bits representing a message packet by concatenating the consecutive sets of data bits, the message packet associated with the encoded message packet and selected from the group consisting of a memory write packet, a memory read packet, and a status interrogation command packet; and

,

a link layer signaling protocol control circuit configured to generate a set of memory transaction signals based on the set of link layer bits, and to provide the set of memory transaction signals to a memory controller.

2. The apparatus of claim 1, wherein the link layer bits comprise 24 bits, and each consecutive set of bits comprises 3 data bits.

3. The apparatus of claim 1, wherein the message packet is a Kandou Memory Link (KML) packet.

4. The apparatus of claim 1, wherein the vector signaling code is an H4 code.

5. The apparatus of claim 1, wherein the consecutive sets of symbols of codewords are self-clocking.

6. The apparatus of claim 1, wherein:

the link layer signaling protocol control circuit is further configured to receive a second set of memory transaction signals from the memory controller and to responsively generate a second set of link layer bits representing the second set of memory transaction signals as a second message packet, wherein the second message packet is selected from the group consisting of a memory write complete packet, a memory read result packet, a status response packet, and an error report message packet; and

,

wherein the physical layer signaling protocol control circuit is further configured to receive the second set of link layer bits, to select a set of data bits from the link layer bits, to form a transmission codeword of the vector signaling code based on the selected set of data bits, the code word comprising a second set of symbols, to map the second set of symbols of the transmission codeword to the collection of interconnection signal lines and to synchronize symbol communication via symbol clock lines.

7. The apparatus of claim 6, wherein the collection of interconnection signal lines comprises four bidirectional data lines and two symbol clock lines.

8. The apparatus of claim 7, wherein the physical layer signaling protocol control circuit communicates three data bits over the four data lines using a balanced code of symbols having four distinct signal levels.

9. The apparatus of claim 8, wherein the collection of interconnection signal lines additionally comprises two clock lines carrying a return clock signal to the physical layer signaling protocol control circuit.

10. The apparatus of claim 6, wherein the collection of interconnection lines comprises five bidirectional data lines and two symbol clock lines.

11. A method comprising:

receiving consecutive codewords of a vector signaling code, each codeword represented as a set of symbols received synchronously over-a collection of interconnection signal lines, the consecutive received codewords collectively representing an encoded message packet;

decoding the consecutive sets of symbols of each codeword into consecutive sets of data bits, and forming a set of link layer bits representing the second message packet by concatenating the consecutive sets of data bits, the message packet associated with the encoded message packet and selected from the group consisting of a memory write packet, a memory read packet, and a status interrogation command packet;

generating a set of memory transaction signals based on the set of link layer bits; and

,

providing the set of memory transaction signals to a memory controller.

12. The method of claim 11, wherein the link layer bits comprise 24 bits, and each consecutive set of bits comprises 3 data bits.

13. The method of claim 11, wherein the message packet is a Kandou Memory Link (KML) packet.

14. The method of claim 11, wherein the vector signaling code is an H4 code.

15. The method of claim 11, wherein the consecutive sets of symbols of codewords are self-clocking.

16. The method of claim 11, further comprising:

receiving a second set of memory transaction signals from the memory controller and responsively generating a second set of link layer bits representing the second set of memory transaction signals as a second message packet, wherein the second message packet is selected from the group consisting of a memory write complete packet, a memory read result packet, a status response packet, and an error report message packet;

selecting a set of data bits from the link layer bits, and responsively forming a transmission codeword of the vector signaling code based on the selected set of data bits, the code word comprising a second set of symbols

mapping the second set of symbols of the transmission codeword to the collection of interconnection signal lines; and

,

synchronizing symbol communication via symbol clock lines.

17. The method of claim 16, wherein the collection of interconnection signal lines comprises four bidirectional data lines and two symbol clock lines.

18. The method of claim 17, wherein the physical layer signaling protocol control circuit communicates three data bits over the four data lines using a balanced code of symbols having four distinct signal levels.

19. The method of claim 18, wherein the collection of interconnection signal lines additionally comprises two clock lines carrying a return clock signal to the physical layer signaling protocol control circuit.

20. The method of claim 16, wherein the collection of interconnection lines comprises five bidirectional data lines and two symbol clock lines.