Voltage mode sensing for low power flash memory

• US 9,607,708 B2
• Filed: 10/31/2012
• Issued: 03/28/2017
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Walsh, Kevin K., Patterson, Paul B., Benton, Glen W., Wilkinson, Jeffrey D.
• Primary Examiner(s): King, Douglas
• Application Number:
  US13/665,409
• Publication Number:
  US 20130235663A1
• Time in Patent Office: 1,609 Days
• Field of Search: 365/185.18, 365/185.21, 365/185.23
• US Class Current: 1/1
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

Claims

1. An electrically erasable flash memory, comprising:

a plurality of data storage elements configured to store a plurality of data bits, each of said plurality of data bits having a data state;

a reference storage element in addition to said plurality of storage elements configured to store a reference; and

a voltage sensing circuit selectively coupled to individual ones of said plurality data storage elements and said reference storage element and said voltage sensing circuit being configured to bias said individual ones of said plurality of data storage elements and said reference storage element with a bias resistance and to read said data state of said individual ones of said plurality of data bits stored in said plurality of data storage elements;

wherein an output of said reference from said reference storage element provides an indication that data read out from said plurality of storage elements is valid;

wherein each of said plurality of data storage elements has a performance margin;

wherein said voltage sensing circuit is configured to selectively bias said plurality of data storage elements with said bias being at least one of a read bias and a margin bias; and

wherein, when said voltage sensing circuit biases said individual one of said plurality of data storage elements with said margin bias, said individual one of said plurality of data storage elements induces a response indicative of said performance margin of said individual one of said plurality of data storage elements.

2. The memory of claim 1 wherein said voltage sensing circuit comprises:

a sensor; and

a biasing circuit configured to bias said sensor with said bias resistance;

wherein each of said plurality of data storage elements induces a response in said sensor indicative of said data state of a selected one of said plurality of data storage elements.

3. The memory of claim 1 wherein said voltage sensing circuit comprises:

a sensor; and

a biasing circuit configured to bias said sensor with said bias current;

wherein each of said plurality of data storage elements induces a response in said sensor indicative of said data state of a selected one of said plurality of data storage elements based, at least in part, on said indication from said reference storage element that data read out is valid.

4. The memory of claim 3:

wherein each of said plurality of data storage elements has a performance margin;

wherein said biasing circuit is configured to selectively bias said sensor with said bias current being at least one of a read bias and a margin bias; and

wherein, when said biasing circuit biases said sensor with said margin bias, said individual one of said plurality of data storage elements induces a response in said sensor indicative of said performance margin of said individual one of said plurality of data storage elements.

5. The memory of claim 4 wherein said plurality of data bits comprise binary data bits having two data states.

6. The memory of claim 5:

wherein said biasing circuit is configured to selectively bias said sensor with said margin bias being one of a margin high voltage and a margin low voltage;

wherein, when one of said plurality of data bits is stored in a first of said two data states and said biasing circuit is configured with said margin high voltage, said sensor is indicative of said performance margin of said one of said plurality of data storage elements for data stored in said first of said two data states; and

wherein, when one of said plurality of data bits is stored in a second of said two data states and said biasing circuit is configured with said margin low voltage, said sensor is indicative of said performance margin of said one of said plurality of data storage elements for data stored in said second of said two data states.

7. The memory of claim 5:

wherein said biasing circuit is configured to selectively bias said sensor with said margin bias being one of a margin zero bias and a margin one bias;

wherein, when one of said plurality of data bits is stored in a first of said two data states and said biasing circuit is configured with said margin zero bias, said sensor is indicative of said performance margin of said one of said plurality of data storage elements for data stored in said first of said two data states; and

wherein, when one of said plurality of data bits is stored in a second of said two data states and said biasing circuit is configured with said margin one bias, said sensor is indicative of said performance margin of said one of said plurality of data storage elements for data stored in said second of said two data states.

8. The memory of claim 1:

wherein said plurality of data storage elements are organized into a plurality of bitlines; and

wherein said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines;

wherein said pre-discharge circuit is configured to drive at least one of said plurality of bitlines to a predetermined voltage level prior to said individual one of said plurality of data storage elements inducing said response indicative of said data state in said individual one of said plurality of data bits.

9. The memory of claim 8 wherein each of said plurality of bitlines not corresponding to said individual one of said plurality of data storage elements is driven to said predetermined voltage level.

10. The memory of claim 9 wherein said predetermined voltage level is a reference voltage of at least a portion of said memory.

11. A memory module, comprising:

a flash memory cell operatively coupled to a voltage reference and configured to sink a relatively high amount of current in a first state and a relatively low amount of current in a second state different from said first state;

a reference memory cell in addition to said flash memory cell configured to store a reference;

a bias circuit operatively coupled between a voltage supply and said flash memory cell and said reference memory cell and said bias circuit being configured to form a sensing node between said bias circuit and said flash memory cell and said reference memory cell; and

a sensing circuit operatively coupled to said sensing node configured to voltage bias said flash memory cell with a bias and to read said data state of said flash memory cell based, at least in part, on said bias;

wherein an output of said reference from said reference memory cell provides an indication when to read said data state of said flash memory cell;

wherein said flash memory cell has a performance margin;

wherein said sensing circuit is configured to selectively bias said flash memory cell with said bias being at least one of a read bias and a margin bias; and

wherein, when said sensing circuit biases said flash memory cell with said margin bias, said flash memory cell induces a response indicative of said performance margin of said flash memory cell.

12. The memory module of claim 11 wherein said bias circuit induces a bias resistance on said sensing node and wherein said flash memory cell induces a response in said sensor indicative of said data state of said flash memory cell.

13. The memory module of claim 11 wherein said bias circuit induces a bias current on said sensing node and wherein said memory cell induces a response in said sensor indicative of a data state said flash memory cell.

14. The memory module of claim 13:

wherein said flash memory cell has a performance margin;

wherein said biasing circuit is configured to selectively bias said sensor with said bias current being at least one of a read bias and a margin bias; and

wherein, when said biasing circuit biases said sensor with said margin bias, said flash memory cell induces a response in said sensor indicative of said performance margin of said flash memory cell.

15. The memory module of claim 14 wherein said flash memory cell comprises binary data bits having two data states.

16. The memory module of claim 15:

wherein said biasing circuit is configured to selectively bias said sensor with said margin bias being one of a margin high voltage and a margin low voltage;

wherein, when said flash memory cell is stored in a first of said two data states and said biasing circuit is configured with said margin high voltage, said sensor is indicative of said performance margin of said flash memory cell for data stored in said first of said two data states; and

wherein, when said flash memory cell is stored in a second of said two data states and said biasing circuit is configured with said margin low voltage, said sensor is indicative of said performance margin of said flash memory cell for data stored in said second of said two data states.

17. The memory module of claim 15:

wherein said biasing circuit is configured to selectively bias said sensor with said margin bias being one of a margin zero bias and a margin one bias;

wherein, when said flash memory cell is stored in a first of said two data states and said biasing circuit is configured with said margin zero bias, said sensor is indicative of said performance margin of said flash memory cell for data stored in said first of said two data states; and

wherein, when said flash memory cell is stored in a second of said two data states and said biasing circuit is configured with said margin one bias, said sensor is indicative of said performance margin of said flash memory cell for data stored in said second of said two data states.

18. The memory module of claim 11 further comprising a plurality of flash memory cells operatively coupled to said bias circuit and said sensing circuit:

wherein said plurality of flash memory cell is organized into a plurality of bitlines; and

wherein said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines;

wherein said pre-discharge circuit is configured to drive at least one of said plurality of bitlines to a predetermined voltage level prior to one of said plurality of flash memory cells inducing said response indicative of said data state in said flash memory cell.

19. The memory module of claim 18 wherein each of said plurality of bitlines not corresponding to said one of said plurality of flash memory cells is driven to said predetermined voltage level.

20. The memory module of claim 19 wherein said predetermined voltage level is a reference voltage of at least a portion of said memory.

21. A method of operating an electrically erasable flash memory having a plurality of data storage elements configured to store a plurality of data bits, each of said plurality of data bits having a data state, a reference storage element in addition to said plurality of data storage elements to store a reference and a voltage sensing circuit, comprising the steps of:

selectively coupling individual ones of said plurality data storage elements and said reference storage element to said voltage sensing circuit;

biasing said individual ones of said plurality of data storage elements with a bias; and

then

reading said data state of said individual ones of said plurality of data storage elements when said reference output from said reference storage element is valid and based, at least in part, on a voltage of said individual ones of said plurality of data bits stored in said plurality of data storage elements;

wherein each individual one of said plurality of data storage elements has a performance margin;

wherein said bias is one of a read bias voltage and a margin bias voltage;

wherein said biasing step, for a normal read, selectively biases said plurality of data storage elements to said read bias to determine said data state of said individual one of said plurality of data storage elements;

wherein said biasing step, for a performance margin test, selectively biases said plurality of data storage elements to said margin bias to determine said performance margin of said individual one of said plurality of data storage elements;

further comprising the step of determining whether or not said data state read from said plurality of data storage elements for said performance margin test is a correct data state.

22. The method of claim 21 wherein said biasing step comprises coupling a resistance bias to said individual ones of said plurality of data storage elements to detect a margin high of said individual ones of said plurality of data storage elements.

23. The method of claim 21 wherein said biasing step comprises coupling a resistance bias and a current bias to said individual ones of said plurality of data storage elements to detect a margin low of said individual ones of said plurality of data storage elements.

24. The method of claim 21 wherein said plurality of data bits comprise binary data bits having two data states.

25. The method of claim 24:

selectively biasing said sensor with said margin bias being one of a margin high bias and a margin low bias;

wherein, when one of said plurality of data bits is stored in a first of said two data states and said biasing circuit is configured with said margin high bias, said sensor is indicative of said performance margin of said one of said plurality of data bits for data stored in said first of said two data states; and

wherein, when one of said plurality of data bits is stored in a second of said two data states and said biasing circuit is configured with said margin low voltage, said sensor is indicative of said performance margin of said one of said plurality of data bits for data stored in said second of said two data states.

26. The method of claim 21:

wherein said plurality of data storage elements are organized into a plurality of bitlines; and

wherein said memory further comprises a pre-discharge circuit operatively coupled to said plurality of bitlines;

further comprising the step of driving, with said pre-discharge circuit, at least one of said plurality of bitlines to a predetermined voltage level prior to said individual one of said plurality of data storage elements inducing said response indicative of said data state in said individual one of said plurality of data storage elements.

27. The method of claim 26 further comprising the step of driving each of said plurality of bitlines not corresponding to said individual one of said plurality of data storage elements to said predetermined voltage level.

28. The method of claim 27 wherein said predetermined voltage level is a reference voltage of at least a portion of said memory.