Integrated circuit comprising at least an integrated antenna

• US 9,607,912 B2
• Filed: 07/12/2016
• Issued: 03/28/2017
• Est. Priority Date: 07/28/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto, Finocchiaro, Alessandro
• Primary Examiner(s): Roman, Angel
• Application Number:
  US15/208,269
• Publication Number:
  US 20160322269A1
• Time in Patent Office: 259 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 29/0642 : Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

Claims

1. An integrated circuit, comprising:

a substrate having a top surface;

an insulating region above the top surface, said insulating region including metallizations;

an antenna structure located in an area within scribe lines of the integrated circuit, said antenna structure formed by antenna lines arranged in different planes of said metallizations;

a trench extending at least partially through a thickness of the substrate, said trench located adjacent the antenna structure; and

a magnetic material located within said trench.

2. The integrated circuit of claim 1, further comprising a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent the scribe lines, wherein the antenna structure lies within the peripheral portion.

3. The integrated circuit of claim 2, wherein the trench is extends to a location between the antenna structure and the scribe line.

4. The integrated circuit of claim 2, wherein the trench is extends to a location between the antenna structure and the active circuit area.

5. The integrated circuit of claim 1, wherein said trench includes sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the trench.

6. The integrated circuit of claim 5, further including an insulating material filling a region between the magnetic material that lines said sidewalls.

7. The integrated circuit of claim 1, wherein said trench forms an isolation region within said substrate.

8. An integrated circuit, comprising:

a substrate having a top surface;

an insulating region above the top surface, said insulating region including metallizations;

an antenna structure within a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent a scribe line, said antenna structure formed by antenna lines arranged in different planes of said metallizations;

a first trench extending at least partially through a thickness of the insulating region, said first trench located within the peripheral portion adjacent the antenna structure; and

a magnetic material located within said first trench.

9. The integrated circuit of claim 8, wherein the first trench is positioned between the antenna structure and the scribe line.

10. The integrated circuit of claim 8, wherein the first trench is positioned between the antenna structure and the active circuit area.

11. The integrated circuit of claim 8, wherein said first trench includes sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the first trench.

12. The integrated circuit of claim 11, further including an insulating material filling a region between the magnetic material that lines said sidewalls.

13. The integrated circuit of claim 8, wherein said first trench extends completely through the thickness of the insulating region.

14. The integrated circuit of claim 8, wherein said first trench extends completely through the thickness of the insulating region and penetrates at least partially through the substrate.

15. The integrated circuit of claim 14, further including an isolation region within said substrate, wherein the first trench penetrates into the isolation region.

16. The integrated circuit of claim 8, further including an isolation region within said substrate, wherein said antenna structure and first trench are located above the isolation region.

17. The integrated circuit of claim 16, wherein said first trench extends along a sidewall of the isolation region.

18. The integrated circuit of claim 16, further including a further magnetic material extending along a bottom of the isolation region and in contact with the magnetic material within the first trench.

19. The integrated circuit of claim 16, wherein the isolation region is a through silicon via structure within the substrate and filled with an insulating material.

20. The integrated circuit of claim 16, further comprising:

a second trench extending at least partially through a thickness of the isolation region; and

a further magnetic material located within said second trench.

21. The integrated circuit of claim 20, wherein said second trench includes sidewalls and a bottom, and wherein said further magnetic material lines said sidewalls and bottom of the second trench.

22. The integrated circuit of claim 21, further including an insulating material filling a region between the magnetic material that lines said sidewalls.

23. The integrated circuit of claim 20, wherein said first and second trenches are vertically aligned with each other.

24. An integrated circuit, comprising:

a substrate having a top surface;

an insulating region above the top surface, said insulating region including metallizations;

an antenna structure within a peripheral portion of the integrated circuit that surrounds an active circuit area, said peripheral portion located adjacent a scribe line, said antenna structure formed by antenna lines arranged in different planes of said metallizations;

a first trench extending at least partially through a thickness of the insulating region, said first trench located within the peripheral portion between the antenna structure and the scribe line;

a second trench extending at least partially through the thickness of the insulating region, said second trench located within the peripheral portion between the antenna structure and the active circuit area; and

a magnetic material located within said first and second trenches.

25. The integrated circuit of claim 24, wherein said first and second trenches include sidewalls and a bottom, and wherein said magnetic material lines said sidewalls and bottom of the first and second trenches.

26. The integrated circuit of claim 25, further including an insulating material filling a region between the magnetic material that lines said sidewalls.

27. The integrated circuit of claim 24, wherein said first and second trenches extend completely through the thickness of the insulating region and penetrate at least partially through the substrate.

28. The integrated circuit of claim 27, further including an isolation region within said substrate, wherein the first and second trenches penetrate into the isolation region.

29. The integrated circuit of claim 28, further including a further magnetic material extending along a bottom of the isolation region and in contact with the magnetic material within the first and second trenches.

30. The integrated circuit of claim 24, further including an isolation region within said substrate, wherein said antenna structure and first and second trenches are located above the isolation region.

31. The integrated circuit of claim 30, further including:

a third trench extending at least partially through a thickness of the isolation region, said third trench positioned in vertical alignment with the first trench between the antenna structure and the scribe line;

a fourth trench extending at least partially through the thickness of the isolation region, said fourth trench positioned in vertical alignment with the second trench between the antenna structure and the active circuit area; and

a further magnetic material located within said third and fourth trenches.

32. The integrated circuit of claim 31, wherein said third and fourth trenches include sidewalls and a bottom, and wherein said further magnetic material lines said sidewalls and bottom of the third and fourth trenches.

33. The integrated circuit of claim 32, further including an insulating material filling a region between the further magnetic material that lines said sidewalls.