Multi-chip semiconductor package with via components and method for manufacturing the same
First Claim
1. A multi-chip semiconductor package, comprising:
- a lower RDL interposer having a first side, a second side opposite to the first side, and a first sidewall surface extending between the first side and the second side;
a first chip mounted on the first side within a chip mounting area of the lower RDL interposer;
a plurality of via components mounted on the first side only within a peripheral area being adjacent to the chip mounting area of the lower RDL interposer, wherein the via components and the first chip are coplanar, wherein each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion;
a first molding compound disposed on the first side, the first molding compound surrounding the first chip and the via components, wherein the first molding compound has a second sidewall surface;
a plurality of solder bumps mounted on the second side of the lower RDL interposer;
an upper RDL interposer being integrally constructed on the first chip, the via components, and on the first molding compound and being electrically connected to the connection portion of each of the via components, wherein the upper RDL interposer has a third sidewall surface, and wherein there is no air gap disposed between the upper RDL interposer and the lower RDL interposer;
a second chip mounted on the upper RDL interposer; and
a second molding compound surrounding the second chip, wherein the second molding compound has a fourth sidewall surface, and wherein the first sidewall surface, the second sidewall surface, the third sidewall surface, and the fourth sidewall surface are contiguous and flush with one another.
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Abstract
A multi-chip semiconductor package includes a lower RDL interposer, a first chip on the lower RDL interposer within a chip mounting area, via components mounted within a peripheral area, and a first molding compound surrounding the first chip and the via components. Each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion. An upper RDL interposer is integrally constructed on the first chip, on the via components, and on the first molding compound. The upper RDL interposer is electrically connected to the connection portion of each of the via components. A second chip is mounted on the upper RDL interposer. A second molding compound surrounds the second chip.
81 Citations
19 Claims
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1. A multi-chip semiconductor package, comprising:
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a lower RDL interposer having a first side, a second side opposite to the first side, and a first sidewall surface extending between the first side and the second side; a first chip mounted on the first side within a chip mounting area of the lower RDL interposer; a plurality of via components mounted on the first side only within a peripheral area being adjacent to the chip mounting area of the lower RDL interposer, wherein the via components and the first chip are coplanar, wherein each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion; a first molding compound disposed on the first side, the first molding compound surrounding the first chip and the via components, wherein the first molding compound has a second sidewall surface; a plurality of solder bumps mounted on the second side of the lower RDL interposer; an upper RDL interposer being integrally constructed on the first chip, the via components, and on the first molding compound and being electrically connected to the connection portion of each of the via components, wherein the upper RDL interposer has a third sidewall surface, and wherein there is no air gap disposed between the upper RDL interposer and the lower RDL interposer; a second chip mounted on the upper RDL interposer; and a second molding compound surrounding the second chip, wherein the second molding compound has a fourth sidewall surface, and wherein the first sidewall surface, the second sidewall surface, the third sidewall surface, and the fourth sidewall surface are contiguous and flush with one another. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification