Semiconductor device

• US 9,607,991 B2
• Filed: 08/28/2014
• Issued: 03/28/2017
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Aoki, Takeshi
• Primary Examiner(s): King, Joshua
• Assistant Examiner(s): Alam, Mohammed R
• Application Number:
  US14/471,151
• Publication Number:
  US 20150060978A1
• Time in Patent Office: 943 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a first electrode, a second electrode, and a third electrode over the semiconductor layer, wherein the second electrode is between the first electrode and the third electrode;

a first insulating film over the first electrode;

a second insulating film over the semiconductor layer, in a first region between the first electrode and the second electrode;

a third insulating film over the semiconductor layer, in a second region between the second electrode and the third electrode;

a fourth insulating film over the third electrode;

a first wiring overlapping the semiconductor layer with the first electrode and the first insulating film therebetween;

a second wiring overlapping the semiconductor layer with the second insulating film therebetween;

a third wiring overlapping the semiconductor layer with the third insulating film therebetween;

a fourth wiring overlapping the semiconductor layer with the third electrode and the fourth insulating film therebetween;

a fifth insulating film over the first wiring, the second wiring, the third wiring, and the fourth wiring; and

a fifth wiring over the fifth insulating film and electrically connected to the second electrode through a contact hole in the fifth insulating film,

wherein the first wiring, the second wiring, the third wiring, and the fourth wiring are parallel to one another, and

wherein the fifth wiring is perpendicular to the first wiring.

2. The semiconductor device according to claim 1, wherein the first electrode faces a top surface of the semiconductor layer and a side surface of the semiconductor layer.

3. The semiconductor device according to claim 1, wherein the first wiring faces a top surface of the semiconductor layer and a side surface of the semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the second wiring is electrically connected to a word line driver circuit, and

wherein the fifth wiring is electrically connected to a bit line driver circuit.

5. The semiconductor device according to claim 1, wherein the contact hole is located between the second wiring and the third wiring.

6. The semiconductor device according to claim 1, wherein each of the first electrode, the second electrode, and the third electrode is in contact with the semiconductor layer.

7. The semiconductor device according to claim 1, further comprising an interlayer insulating film over the second insulating film, wherein the fifth wiring is located over the interlayer insulating film.

8. The semiconductor device according to claim 1, wherein the second wiring partly overlaps the first electrode and the second electrode.

9. The semiconductor device according to claim 1, wherein the semiconductor layer comprises indium and zinc.

10. The semiconductor device according to claim 1, wherein the first wiring overlaps the semiconductor layer, and wherein the fourth wiring overlaps the semiconductor layer.

11. A semiconductor device comprising:

a first memory cell and a second memory cell each comprising a transistor and a capacitor; and

an insulating film over the transistor of the first memory cell and the transistor of the second memory cell,

wherein the transistors of the first memory cell and the second memory cell share a drain electrode,

wherein a first capacitor line is electrically connected to the capacitor in the first memory cell,

wherein a second capacitor line is electrically connected to the capacitor in the second memory cell,

wherein the transistor of the first memory cell and the transistor of the second memory cell comprise a common semiconductor layer over an insulating surface,

wherein the insulating film is in contact with the insulating surface,

wherein the drain electrode shared by the first memory cell and the second memory cell is electrically connected to a bit line through a contact hole located over the shared drain electrode and between the capacitor in the first memory cell and the capacitor in the second memory cell, and

wherein the bit line is located over the first capacitor line and the second capacitor line.

12. The semiconductor device according to claim 11, wherein the first capacitor line and the second capacitor line are located over the common semiconductor layer.

13. The semiconductor device according to claim 11, wherein the common semiconductor layer comprises indium and zinc.