Semiconductor device with isolated body portion

• US 9,608,059 B2
• Filed: 12/20/2011
• Issued: 03/28/2017
• Est. Priority Date: 12/20/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Cappellani, Annalisa, Cea, Stephen M., Ghani, Tahir, Gomez, Harry, Kavalieros, Jack T., Keys, Patrick H., Kim, Seiyon, Kuhn, Kelin J., Lilak, Aaron D., Rios, Rafael, Sahni, Mayank
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Prasad, Neil
• Application Number:
  US13/995,418
• Publication Number:
  US 20130320455A1
• Time in Patent Office: 1,925 Days
• Field of Search: 257/368, 438/294
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76216 introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

Claims

1. A semiconductor device, comprising:

a semiconductor body disposed above a semiconductor substrate, the semiconductor body having a first width and comprising a channel region and a pair of source and drain regions on either side of the channel region;

an isolation pedestal disposed between the semiconductor body and the semiconductor substrate, the isolation pedestal having a second width parallel with, and less than, the first width, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and

a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

2. The semiconductor device of claim 1, wherein the isolation pedestal is disposed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

3. The semiconductor device of claim 1, wherein the isolation pedestal is disposed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

4. The semiconductor device of claim 1, wherein the isolation pedestal is disposed below the pair of source and drain regions and below the channel region of the semiconductor body.

5. The semiconductor device of claim 1, wherein the isolation pedestal is notched with rounded edges beneath the semiconductor body.

6. The semiconductor device of claim 1, wherein the isolation pedestal is notched with faceted edges beneath the semiconductor body.

7. The semiconductor device of claim 1, further comprising:

a first dielectric layer disposed adjacent to the isolation pedestal and above the semiconductor substrate.

8. The semiconductor device of claim 7, further comprising:

a second dielectric layer disposed below the first dielectric layer and on the semiconductor substrate.

9. The semiconductor device of claim 1, wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric.

10. The semiconductor device of claim 1, further comprising:

one or more nanowires disposed vertically above the semiconductor body, wherein the gate electrode stack at least partially surrounds a portion of each of the one or more nanowires.

11. A semiconductor device, comprising:

a semiconductor body disposed above a semiconductor substrate, the semiconductor body comprising a first semiconductor material, and comprising a channel region and a pair of source and drain regions on either side of the channel region;

an isolation pedestal disposed between the semiconductor body and the semiconductor substrate, the isolation pedestal comprising an oxide of a second semiconductor material different from the first semiconductor material, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and

a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

12. The semiconductor device of claim 11, wherein the isolation pedestal is disposed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

13. The semiconductor device of claim 11, wherein the isolation pedestal is disposed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

14. The semiconductor device of claim 11, wherein the isolation pedestal is disposed below the pair of source and drain regions and below the channel region of the semiconductor body.

15. The semiconductor device of claim 11, wherein the semiconductor body consists essentially of silicon, and the second semiconductor material is silicon germanium.

16. The semiconductor device of claim 11, further comprising:

a dielectric layer disposed adjacent to the isolation pedestal and above the semiconductor substrate.

17. The semiconductor device of claim 16, further comprising:

a second dielectric layer disposed below the first dielectric layer and on the semiconductor substrate.

18. The semiconductor device of claim 11, wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric.

19. The semiconductor device of claim 11, further comprising:

one or more nanowires disposed vertically above the semiconductor body, wherein the gate electrode stack at least partially surrounds a portion of each of the one or more nanowires.

20. The semiconductor device of claim 11, wherein the semiconductor body has a first width, and the isolation pedestal has a second width parallel with and less than the first width.

21. The semiconductor device of claim 20, wherein the isolation pedestal is notched with rounded edges beneath the semiconductor body.

22. The semiconductor device of claim 20, wherein the isolation pedestal is notched with faceted edges beneath the semiconductor body.

23. A method of fabricating a semiconductor device, the method comprising:

forming a semiconductor body above a semiconductor substrate, the semiconductor body comprising a channel region and a pair of source and drain regions on either side of the channel region;

forming an isolation pedestal between the semiconductor body and the semiconductor substrate, wherein the semiconductor body has a first width and the isolation pedestal is formed from a second width parallel with and less than the first width or wherein the semiconductor body comprises a first semiconductor material and the isolation pedestal comprises an oxide of a second semiconductor material different from the first semiconductor material, wherein the isolation pedestal is an electrically insulating isolation pedestal, the isolation pedestal completely electrically isolating the semiconductor body from the semiconductor substrate; and

forming a gate electrode stack at least partially surrounding a portion of the channel region of the semiconductor body.

24. The method of claim 23, wherein the isolation pedestal is formed below the channel region, but not below the pair of source and drain regions, of the semiconductor body.

25. The method of claim 23, wherein the isolation pedestal is formed below the pair of source and drain regions, but not below the channel region, of the semiconductor body.

26. The method of claim 23, wherein the isolation pedestal is formed below the pair of source and drain regions and below the channel region of the semiconductor body.

27. The method of claim 23, further comprising:

forming a first dielectric layer adjacent to the isolation pedestal and above the semiconductor substrate.

28. The method of claim 27, further comprising:

forming a second dielectric layer below the first dielectric layer and on the semiconductor substrate.