Method and apparatus for MOS device with doped region

• US 9,608,107 B2
• Filed: 02/27/2014
• Issued: 03/28/2017
• Est. Priority Date: 02/27/2014
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Lee, Tsung-Hsiung, Lin, Shin-Cheng
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): CIESLEWICZ, ANETA B
• Application Number:
  US14/192,097
• Publication Number:
  US 20150243783A1
• Time in Patent Office: 1,125 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a doped well disposed in the semiconductor layer and having a first conductivity type;

a drain region disposed in the doped well;

a source region and a body region disposed in the semiconductor layer;

a first doped region having a second conductivity type, the first doped region being disposed between the source region and the doped well, and a lower portion of the first doped region being in contact with the semiconductor layer;

a second doped region having the first conductivity type, the second doped region being disposed under the source region and between the source region and the first doped region, and a lower portion of the second doped region being in contact with the semiconductor layer;

a third doped region having the second conductivity type and disposed in the doped well; and

a fourth doped region disposed in the doped well and above the third doped region, the fourth doped region having the first conductivity type.

2. The semiconductor device according to claim 1, further comprising

a fifth doped region having the second conductivity type and disposed under the body region.

3. The semiconductor device according to claim 2, wherein

the first doped region and the fifth doped region have substantially the same doping concentration.

4. The semiconductor device according to claim 2, wherein the first doped region and the fifth doped region have different doping concentrations.

5. The semiconductor device according to claim 1, further comprising

a field plate connected to at least one of the source region, the drain region, or the body region.

6. The semiconductor device according to claim 2, further comprising

a field plate connected to at least one of the source region, the drain region, or the body region.

7. The semiconductor device according to claim 1, further comprising

an insulator disposed on the first doped region;

and

a conductive member disposed on the insulator.

8. The semiconductor device according to claim 7, further comprising

a field plate connected to the conductive member.

9. The semiconductor device according to claim 2, further comprising

an insulator disposed on the first doped region;

and

a conductive member disposed on the insulator.

10. The semiconductor device according to claim 9, further comprising

a field plate connected to the conductive member.

11. A semiconductor device comprising:

a semiconductor layer;

a doped well disposed in the semiconductor layer and having a first conductivity type;

a drain region disposed in the doped well;

a source region and a body region disposed in the semiconductor layer;

a first doped region having a second conductivity type, the first doped region being disposed between the source region and the doped well, and a lower portion of the first doped region being in contact with the semiconductor layer; and

a second doped region having the first conductivity type, the second doped region being disposed under the source region and between the source region and the first doped region, and a lower portion of the second doped region being in contact with the semiconductor layer.

12. The semiconductor device according to claim 11, further comprising

a third doped region having the second conductivity type and disposed under the body region.

13. The semiconductor device according to claim 12, wherein

the first doped region and the third doped region have substantially the same doping concentration.

14. The semiconductor device according to claim 12, wherein

the first doped region and the third doped region have different doping concentrations.

15. The semiconductor device according to claim 11, further comprising

a field plate connected to at least one of the source region, the drain region, or the body region.

16. The semiconductor device according to claim 12, further comprising

a field plate connected to at least one of the source region, the drain region, or the body region.

17. The semiconductor device according to claim 11, further comprising

an insulator disposed on the first doped region;

and

a conductive member disposed on the insulator.

18. The semiconductor device according to claim 17, further comprising

a field plate connected to the conductive member.

19. The semiconductor device according to claim 12, further comprising

an insulator disposed on the first doped region;

and

a conductive member disposed on the insulator.

20. The semiconductor device according to claim 19, further comprising

a field plate connected to the conductive member.