Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for tracking supply, temperature, and/or process variation

• US 9,608,630 B2
• Filed: 05/06/2009
• Issued: 03/28/2017
• Est. Priority Date: 05/06/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hollis, Timothy M.
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US12/436,683
• Publication Number:
  US 20100283503A1
• Time in Patent Office: 2,883 Days
• Field of Search: 326/21, 326/26, 326/30, 326 81- 83, 326 86- 87, 327108-109
• US Class Current: 1/1
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar to the ODT circuit. In some embodiments an update scheme is provide for the ODT circuit and the Vref circuit to enable simultaneous update of each circuit through the same digital codes.

Claims

1. A memory device, comprising:

an on-die termination circuit (ODT); and

a reference voltage circuit, wherein the reference voltage circuit tracks changes in supply voltage and temperature substantially the same as the on-die termination circuit to produce a variable reference voltage.

2. The device of claim 1, wherein the reference voltage circuit comprises a first series of transistors and a second series of transistors.

3. The device of claim 2, wherein each of the series of transistors comprises

a

pullup leg and a pulldown leg.

4. The device of claim 3, wherein the pullup leg comprises two transistors.

5. The device of claim 4, wherein a reference voltage is generated from between the two transistors of the pullup leg.

6. The device of claim 4, wherein the transistors of the pullup leg comprise PMOS devices, wherein each of the PMOS devices has substantially the same channel resistance.

7. The device of claim 3, wherein the pulldown leg comprises a transistor.

8. The device of claim 7, wherein an impedance of the pulldown leg approximates a nominal pulldown characteristic of an off-chip driver (OCD) of a transmitter that is communicatively coupled to the device.

9. The device of claim 8, wherein the pullup leg and the pulldown leg are configured to match a relative impedance of the ODT circuit and the OCD of the transmitter over digital codes used to achieve a desired impedance of the ODT circuit.

10. A memory device, comprising:

an on-die termination circuit (ODT) comprising a first path having one or more transistors; and

a reference voltage (Vref) circuit comprising a second path having a plurality of transistors, wherein the path of the ODT circuit and the path of the Vref circuit have substantially the same impedance;

wherein the reference voltage circuit produces a variable reference voltage.

11. A device, comprising:

a reference voltage circuit compatible with on-die termination (ODT), comprising a pullup leg, the pullup leg comprising a first transistor and a second transistor, wherein a variable reference voltage is generated from between each of the transistors.

12. The memory device of claim 11, wherein the first and second transistors comprise a first PMOS device and a second PMOS device, respectively, wherein the reference voltage signal is generated from a voltage divided between the first PMOS device and the second PMOS device.

13. The device of claim 12, comprising an other pullup leg, wherein the other pullup leg comprises a third PMOS device and a fourth PMOS device, wherein the reference voltage signal is also generated from the voltage divided between the third PMOS device and the fourth PMOS device.

14. The device of claim 11, comprising a receiver circuit.

15. The device of claim 14, wherein the receiver circuit comprises a latch configured to latch the reference voltage signal and an incoming signal formed across the receiver circuit.

16. The device of claim 11, wherein the device is a memory device.

17. A device, comprising:

a first distribution path coupled to an on-die termination (ODT) circuit; and

a second distribution path coupled to a reference voltage circuit,

wherein updates to the ODT circuit and the reference voltage circuit are substantially simultaneously provided to the ODT circuit and the reference voltage circuit, and wherein the reference voltage circuit produces a variable reference voltage.

18. The device of claim 17, wherein the updates comprise a set of codes for modifying the impedance of the ODT circuit.

19. The memory device of claim 17, further comprising a latch configured to latch an incoming signal formed across the ODT circuit and a reference voltage signal generated by the reference voltage circuit.

20. A method of operating a device, comprising:

providing a first update to an on-die termination (ODT) circuit on a first distribution path;

providing a second update to a reference voltage circuit, wherein the first update and second update are provided to the ODT circuit and the reference voltage circuit, substantially simultaneously, and wherein the reference voltage circuit produces a variable reference voltage.

21. The method of claim 20, wherein substantially simultaneously providing the first and second updates comprises substantially simultaneously providing the first updates to the ODT circuit and the second update to the reference voltage circuit such that an impedance of the reference voltage circuit and an impedance of the ODT circuit are substantially the same.

22. The method of claim 21, wherein the first update comprises a first set of digital codes and the second update comprises the first set of digital codes.

23. The method of claim 20, wherein the first update comprises a first set of digital codes and the second update comprises a second set of digital codes.

24. The method of claim 20, comprising maintaining the same approximate ratio between an impedance of the ODT circuit and an impedance of the reference voltage circuit via the first and second updates respectively.