Detecting satellite signals by storing signal sets spanning code period

• US 9,612,339 B2
• Filed: 03/05/2012
• Issued: 04/04/2017
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nayyar, Jasbir Singh, Tangudu, Jawaharlal, Ganesan, Aravind
• Primary Examiner(s): Gregory, Bernarr
• Assistant Examiner(s): Mull, Fred H
• Application Number:
  US13/412,281
• Publication Number:
  US 20130229305A1
• Time in Patent Office: 1,856 Days
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence

Abstract

A GNSS receiver configured to detect a presence of at least one GNSS satellite signal in a received signal is provided. The GNSS receiver includes a buffer loaded with sample sets corresponding to the received signal and a Doppler derotation block configured to perform a Doppler derotation corresponding to at least one Doppler frequency on a sample set received from the buffer. The GNSS receiver further includes an accumulator block configured to perform a coherent accumulation of a plurality of sample sets upon or subsequent to the Doppler derotation corresponding to a Doppler frequency, and, a first memory configured to store the results of the coherent accumulation. A register array is configured to be loaded with the results stored in the first memory and a correlator engine is configured to generate correlation results by correlating the results in the register array with a plurality of code phases of GNSS satellites.

Claims

1. A process of detecting coded signals from satellites in integrated circuitry, each satellite repeatedly transmitting a unique, analog, coded signal of a certain code period, comprising:

(a) receiving in the integrated circuitry the analog, coded signals from the satellites;

(b) converting the analog, coded signals to coded digital signals in analog to digital converter circuitry;

(c) generating quantized samples of the coded digital signals in first quantization circuitry;

(d) storing the quantized samples in a buffer, the storing including storing sample sets with each set including a number of samples of the coded digital signals spanning a code period;

(e) performing a Doppler derotation on a sample set in the buffer in Doppler derotation circuitry;

(f) coherently accumulating Doppler derotated sample sets in accumulator circuitry for a selected coherent accumulation period;

(g) generating a multiple level quantization of the results of the coherently accumulated Doppler derotated sample sets for a coherent accumulation period in second quantization circuitry, including associating each sample within the sample set with a sample bit representation;

(h) loading results of the multiple level quantization to a register array;

(i) correlating with correlation circuitry the results of the multiple level quantization in the register array with plural code phases of the satellite signals;

(j) non-coherently accumulating the correlations in memory; and

(k) searching for the coded digital signals corresponding to one satellite based on the selected coherent accumulation period and a start timing reference.

2. The process of claim 1 in which the certain period is 1 millisecond and a satellite transmits analog, coded signals that include a data bit every 20 milliseconds by modulating every 20 consecutive coded signals.

3. The process of claim 1 including computing a position of the integrated circuitry after detecting the presence of coded signals from four satellites.

4. The process of claim 1 including generating 1023 samples in one set of the coded digital signals.

5. The process of claim 1 including generating 1023×

6 bits in one sample set of the coded digital signals, with 3 bits representing an I value, and 3 bits representing a Q value.

6. The process of claim 1 in which the storing includes storing samples at one sample per chip.

7. The process of claim 1 in which the storing includes storing samples at two samples per chip.

8. The process of claim 1 in which the storing includes storing samples at four samples per chip.

9. The process of claim 1 in which the selected coherent accumulation period is one of 5 milliseconds, 11 milliseconds, or 19 milliseconds.

10. The process of claim 1 in which the selected accumulation period is less than 20 milliseconds.

21. The process of claim 1 in which the generating a multiple level quantization performs a seven level quantization of the samples that associates each sample with a three bit sample representation.

11. An integrated circuit comprising:

receiver circuitry having an input receiving a unique, analog, coded signal of a certain code period transmitted from each of several satellites and having an analog, coded signal output;

analog to digital converter circuitry having an input coupled to analog, coded signal output and having a digital, coded signal output;

first quantization circuitry having an input coupled to the digital, coded signal output and having a quantized digital, coded signal output;

buffer circuitry having an input coupled to the quantized digital, coded signal output, the buffer circuitry being large enough to store sample sets of the quantized digital, coded signals received at the input with each set including a number of samples of the quantized digital, coded signals spanning a code period, and the buffer circuitry having a buffer output;

Doppler derotation circuitry having an input coupled to the buffer output and having a derotation output providing Doppler derotated sample sets of the quantized digital, coded signals;

accumulator circuitry having an input coupled to the derotation output, having an accumulator output providing coherently accumulated Doppler derotated sample sets for a selected coherent accumulation period, and having an accumulator output;

second quantization circuitry having an input coupled to the accumulator output and having a second quantization output, the second quantization circuitry performing a multiple level quantization of the results of the accumulator circuitry;

a register array having an input coupled to the second quantization output to store the results of the second quantization, and having a register output;

correlation circuitry having an input coupled to the register output and having a correlation output, the correlation circuity correlating the results of the second quantization in the register array with plural code phases of the satellite signals;

memory circuitry having an input coupled to the correlation output and storing the correlation results; and

a control sequencing circuitry coupled to the correlation circuitry and the Doppler derotation circuitry, and scheduling a sequence of searches for the satellite signals based on the selected coherent accumulation period and a start timing reference.

12. The integrated circuit of claim 11 in which the certain period is 1 millisecond and a satellite transmits analog coded signals that include a data bit every 20 milliseconds by modulating every 20 consecutive coded signals.

13. The integrated circuit of claim 11 including processing circuitry computing a position of the integrated circuitry after detecting the presence of coded signals from four satellites.

14. The integrated circuit of claim 11 in which the quantization circuitry generates 1023 samples in one set of the coded digital signals.

15. The integrated circuit of claim 11 in which the quantization circuitry generates 1023×

6 bits in one sample set of the coded digital signals, with 3 bits representing an I value, and 3 bits representing a Q value.

16. The integrated circuit of claim 11 in which the buffer circuitry stores samples at one sample per chip.

17. The integrated circuit of claim 11 in which the buffer circuitry stores samples at two samples per chip.

18. The integrated circuit of claim 11 in which the buffer stores samples at four samples per chip.

19. The integrated circuit of claim 11 in which the selected coherent accumulation period is one of 5 milliseconds, 11 milliseconds, or 19 milliseconds.

20. The integrated circuit of claim 11 in which the selected accumulation period is less than 20 milliseconds.

22. The integrated circuit of claim 11 in which the second quantization circuitry associates each sample within the sample set with a sample bit representation to perform a seven level quantization of the samples associating each sample with a three bit sample representation.