Peripheral watchdog timer

• US 9,612,893 B2
• Filed: 05/11/2015
• Issued: 04/04/2017
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: David, Thomas Saroshan
• Primary Examiner(s): BUTLER, SARAI E
• Application Number:
  US14/709,204
• Publication Number:
  US 20160335149A1
• Time in Patent Office: 694 Days
• Field of Search: 714 55
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0706 the processing taking place on a specific hardware platform or in a specific software environment
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

In some embodiments, a circuit may include a plurality of peripherals and a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals. The peripheral watchdog timer circuit may be configured to reset a count in response to detecting the activity. In some embodiments, the peripheral watchdog timer circuit may be configured to generate an alert signal when the count exceeds a threshold count before detecting the activity. In some embodiments, the peripheral watchdog timer circuit is configured to initiate a reset operation when the alert is not serviced within a period of time.

Claims

1. A circuit comprising:

a plurality of peripherals; and

a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals, the peripheral watchdog timer circuit configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals, the peripheral watchdog timer circuit configured to reset a count in response to detecting the activity.

2. The circuit of claim 1, wherein the peripheral watchdog timer circuit is configured to generate an alert signal when the count exceeds a threshold count before detecting the activity.

3. The circuit of claim 2, wherein:

the alert signal includes an interrupt; and

the peripheral watchdog timer circuit is configured to initiate a reset operation when the interrupt is not serviced within a period of time.

4. The circuit of claim 1, wherein the at least one of the plurality of peripherals comprises an autonomous peripheral configured to operate independently from a processor core, the autonomous peripheral including at least one of a programmable counter, a sensor, and an error detection circuit.

5. The circuit of claim 1, wherein the peripheral watchdog timer circuit is configured to monitor a chain of events associated with at least one peripheral and to generate an alert signal when the count exceeds a threshold count before the chain of events is completed.

6. The circuit of claim 5, further comprising a control circuit coupled to the peripheral watchdog timer circuit and configured to reset at least one of a processor and a peripheral in response to the alert signal.

7. The circuit of claim 5, further comprising a control circuit coupled to the peripheral watchdog timer circuit and, in response to the alert signal, the control circuit configured to investigate the at least one of the plurality of peripherals to determine a state, and optionally to determine a suitable response to reset at least one of the plurality of peripherals.

8. A circuit comprising:

a plurality of peripherals; and

a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals, the peripheral watchdog timer circuit configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality of peripherals, the peripheral watchdog timer circuit configured to generate an alert signal when a count exceeds a threshold count before detecting the activity.

9. The circuit of claim 8, wherein:

the alert signal includes an interrupt; and

the peripheral watchdog timer circuit is configured to initiate a reset operation when the interrupt is not serviced within a period of time.

10. The circuit of claim 8, wherein the peripheral watchdog timer circuit is configured to reset the count in response to detecting the activity.

11. The circuit of claim 8, further comprising a processor core coupled to the plurality of peripherals and to the peripheral watchdog timer circuit, the processor core configured to reset in response to the alert signal.

12. The circuit of claim 8, further comprising:

a control circuit coupled to the peripheral watchdog timer circuit; and

wherein, in response to the alert signal, the control circuit is configured to;

investigate at least one of the plurality of peripherals to determine a state; and

selectively reset at least one of a processor and the peripheral in response to determining the state.

13. The circuit of claim 8, wherein the at least one of the plurality of peripherals comprises an autonomous peripheral configured to operate independently from a processor core.

14. The circuit of claim 8, wherein the peripheral watchdog timer circuit is configured to monitor a chain of events associated with at least one peripheral and to generate the alert signal when the count exceeds the threshold count before the chain of events is completed.

15. A method comprising:

adjusting a count of a peripheral watchdog timer circuit in response to a clock signal;

monitoring at least one peripheral circuit to detect activity; and

generating an alert signal when the count crosses a threshold before detecting the activity.

16. The method of claim 15, wherein adjusting the count comprises decrementing the count in response to each clock cycle of the clock signal.

17. The method of claim 15, wherein adjusting the count comprises incrementing the count in response to each clock cycle of the clock signal.

18. The method of claim 15, further comprising resetting the count when the activity is detected before the count crosses the threshold.

19. The method of claim 15, wherein monitoring at least one peripheral circuit comprises:

monitoring a chain of operations associated with at least one peripheral circuit, the chain including receipt of a triggering signal, consumption of the triggering signal to produce data, and movement of the data to a memory; and

generating the alert signal when the count crosses the threshold before the chain of operations is completed.

20. The method of claim 15, further comprising:

monitoring an interrupt associated with the alert to determine when the interrupt is serviced; and

initiating a reset operation when the interrupt is not serviced within a period of time.

21. The method of claim 15, further comprising:

investigating the at least one peripheral circuit to determine a state; and

selectively initiating one of an interrupt operation to wake a processor to reset the at least one peripheral and a reset operation to reset the at least one peripheral.