Network processor with distributed trace buffers

• US 9,612,934 B2
• Filed: 10/28/2011
• Issued: 04/04/2017
• Est. Priority Date: 10/28/2011
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Dobbie, Bradley D., Asher, David H., Kessler, Richard E.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US13/284,289
• Publication Number:
  US 20130111073A1
• Time in Patent Office: 1,985 Days
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 3/16 Sound input; Sound output speech processing G10L

Abstract

A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.

Claims

1. A system comprising:

a cache; and

a plurality of processor subsets configured to access the cache, each processor subset comprising;

a group of processors;

a bus, the groups connected to the cache via the respective bus, the bus carrying commands from the group of processors to the cache, the bus further carrying data between the cache and the processors; and

a trace buffer connected to the bus between the group of processors and the cache, the trace buffer configured to store information regarding commands to access the cache sent by the group of processors along the bus to the cache, the information including address information, command information and command time information;

the trace buffers at each of the processor subsets sharing a common address space to enable access to the trace buffers as a single entity.

2. The system of claim 1, further comprising a control circuit connected to the bus of each or the plurality of processor subsets, the control circuit configured to direct the command and data signals between the cache and the processors.

3. The system of claim 2, wherein the trace buffer of at least one of the plurality of processor subsets is connected to the bus between the respective processor and the control circuit.

4. The system of claim 2, wherein the trace buffer of at least one of the plurality of processor subsets is connected to the bus between the control circuit and the cache.

5. The system of claim 1, wherein the trace buffer is configured to issue a notification through at least one of a central interrupt unit (CIU) and a wire pulse in response to an event.

6. The system of claim 5, wherein the event is one or more of a captured command signal and an exceeding of a buffer threshold.

7. The system of claim 1, wherein the trace buffers at each of the processor subsets are configured with a common entity identifier, the address space associated with the entity identifier being divided among the trace buffers.

8. A system comprising:

a cache having a plurality of banks and a control circuit configured to direct access requests to the plurality of banks;

a plurality of processor groups, each of the processor groups including a plurality of processors connected to the cache by a respective bus, the bus carrying commands from the group of processors to the cache, the bus further carrying data between the cache and the processors; and

a plurality of trace buffers configured to store information regarding commands to access the cache sent by the plurality of processor groups along the bus to the cache, the information including address information, command information and command time information;

the plurality of trace buffers being adapted to be reconfigurable between a first mode and a second mode, the first mode placing each of the plurality of trace buffers in the path of a different bus between the plurality of processor groups and the control circuit, the second mode placing the plurality of trace buffers between the control circuit and plurality of banks.

9. The system of claim 8, wherein the plurality of trace buffers share a common address space to enable access to the trace buffers as a single entity.

10. The system of claim 8, wherein the plurality of trace buffers are configured to issue a notification through at least one of a central interrupt unit (CIU) and a wire pulse in response to an event.

11. The system of claim 10, wherein the event is one or more of a captured command signal and an exceeding of a buffer threshold.

12. The system of claim 8, wherein the plurality of trace buffers are configured with a common entity identifier, the address space associated with the entity identifier being divided among the trace buffers.